ICS874001AGI-05LF Datasheet, PDF (6/18 Pages) Integrated Device Technology – PCI Express™ Jitter Attenuator

ICS74001I-05 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
AC Electrical Characteristics
Table 5. AC Characteristics, V_DD = V_DDO = 3.3V ± 0.3V, T_A = -40°C to 85°C
Symbol
Parameter
Test Conditions
f_OUT
tjit(cc)
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
100MHz output,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
T_j
(PCIe Gen 1)
Phase Jitter Peak-to-Peak;
NOTE 2, 4
125MHz output,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
250MHz output,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
500MHz, (1.2MHz –21.9MHz),
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
100MHz output,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
T_{REFCLK_HF_RMS} Phase Jitter RMS;
(PCIe Gen 2)
NOTE 3, 4
125MHz output,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
250MHz output,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
500MHz output,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
100MHz output,
Low Band: 10kHz - 1.5MHz
T_{REFCLK_LF_RMS} Phase Jitter RMS;
(PCIe Gen 2)
NOTE 3, 4
125MHz output,
Low Band: 10kHz - 1.5MHz
250MHz output,
Low Band: 10kHz - 1.5MHz
500MHz output,
Low Band: 10kHz - 1.5MHz
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
F_SEL[10] ≠ 11
F_SEL[10] = 11
Minimum
98
200
48
42
Typical
16.14
15.64
13.16
12.17
1.4
1.39
1.18
1.11
0.33
0.22
0.22
0.22
Maximum
640
50
600
52
58
Units
MHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 10⁶ clock periods.
NOTE 3: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t_{REFCLK_HF_RMS}
(High Band) and 3.0ps RMS for t_{REFCLK_LF_RMS} (Low Band).
NOTE 4: Guaranteed only when input clock source is PCI Express and PCI Express Gen 2 compliant.
ICS874001AGI-05 REVISION A JANUARY 14, 2011
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©2011 Integrated Device Technology, Inc.