ICS874001AGI-05LF Datasheet, PDF (13/18 Pages) Integrated Device Technology – PCI Express™ Jitter Attenuator

ICS74001I-05 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Schematic Layout
Figure 4 shows an example of ICS874001I-05 application schematic.
In this example, the device is operated at V_DD = V_DDA = V_DDO = 3.3V.
The input is driven by a 3.3V LVPECL driver.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The ICS74001I-05 provides separate
power supplies to isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
VDDO
U1
VDD
VDDA
10 R1
C2
C3
10u
0.1u
Logic Control Input Examples
Set Logic
Set Logic
VDD _{Input to} VDD _{Input to}
'1'
'0'
RU1
RU2
1K
Not Install
PLL_SEL
MR
F_SEL1
F_SEL0
VDD
1
2
3
4
PLL_SEL
nc
nc
5
6
7
8
nc
MR
nc
F_SEL1
9
10
VDDA
F_SEL0
VDD
C4
0.01u
Zo = 50 Ohm
Zo = 50 Ohm
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
LVPECL Driv er
C1
0.1u
nc
VDDO
Q
20
19
18
17
nQ
nc
nc
GND
16
15
14
13
nCLK
CLK
OE
12
11
Q
nQ
GND
nCLK
CLK
OE
Zo_Dif f = 100 Ohm
LVDS Termination
CLK
nCLK
R4
R5
50
50
R7
50
Q
R3
50
Zo_Dif f = 100 Ohm
C5
0.1uF
R6
50
nQ
+
R2
100
-
+
-
3.3V
BLM18BB221SN1
1
2
VDD
Ferrite Bead
C6
0.1uF
C7
10uF
3.3V
BLM18BB221SN2
1
2
VDDO
Ferrite Bead
C8
0.1uF
C9
10uF
Alternate
LVDS
Termination
Figure 4. ICS874001I-05 Schematic Layout
ICS874001AGI-05 REVISION A JANUARY 14, 2011
13
©2011 Integrated Device Technology, Inc.