ICS874001AGI-05LF Datasheet, PDF (2/18 Pages) Integrated Device Technology – PCI Express™ Jitter Attenuator

ICS74001I-05 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Table 1. Pin Descriptions
Number
Name
Type
Description
1
PLL_SEL
Input
Pullup
PLL select pin. When LOW, bypasses the PLL. When HIGH selects the PLL.
LVCMOS/LVTTL interface levels. See Table 3B.
2, 3, 4, 6,
15, 16, 20
nc
Unused
No connect.
Active High Master Reset. When logic HIGH, the internal dividers are reset
5
MR
Input
Pulldown
causing the true output Q to go LOW and the inverted output nQ to go HIGH.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
7
F_SEL1
Input
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C.
8
V_DDA
Power
Analog supply pin.
9
F_SEL0
Input
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C.
10
V_DD
Power
Core supply pin.
11
OE
Input
Pullup
Output enable. When HIGH, outputs are enabled. When LOW, forces outputs
to a High-Impedance state. LVCMOS/LVTTL interface levels. See Table 3A.
12
CLK
Input
Pulldown Non-inverting differential clock input.
13
nCLK
Input
Pullup
Inverting differential clock input.
14
GND
Power
Power supply ground.
17, 18
nQ, Q
Output
Differential output pair. LVDS interface levels.
19
V_DDO
Power
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
ICS874001AGI-05 REVISION A JANUARY 14, 2011
2
©2011 Integrated Device Technology, Inc.