ICS870S208 Datasheet, PDF (6/20 Pages) Integrated Device Technology – Glitchless output behavior during input switch

ICS870S208 Data Sheet
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
Switch During an Input Bad Detect
If a CLK_SEL, DIV_SEL, or OE event happens after a clock has
stopped, but before the input bad flag has been set (during the
~200ns detect period) the output change will not take effect until the
internal bad flag has been set. The output will go low after the input
bad flag is set and follow the second period of the new clock input.
Although no glitches will occur, due to the unknown state of the failing
clock, a transition may take up to 1us to execute.
CLK0
CLK1
CLK_SEL
Output
Input Bad
Detect, 200ns
Figure 1G. CLK_SEL with Bad Input Timing Diagram
ICS870S208BKLF REVISION A APRIL 3, 2013
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