ICS870S208 Datasheet, PDF (1/20 Pages) Integrated Device Technology – Glitchless output behavior during input switch

Differential-to-LVCMOS/LVTTL Fanout
Buffer w/Divider and Glitchless Switch
ICS870S208
DATASHEET
General Description
The ICS870S208 is a low skew, eight output LVCMOS / LVTTL
Fanout Buffer with selectable divider. The ICS870S208 has two
selectable inputs that accept a variety of differential input types. The
device provides the capability to suppress any glitch at the outputs of
the device during an input clock switch to enhance clock redundancy
in fault tolerant applications. The low impedance LVCMOS outputs
are designed to drive 50series or parallel terminated transmission
lines. The effective fanout can be increased from 8 to 16 by utilizing
the ability of the outputs to drive two series terminated lines. The
divide select inputs, DIV_SELA and DIV_SELB, control the output
frequency of each bank. The output banks can be independently
selected for ÷1 or ÷2 operation. The output enable pins assigned to
each output, support enabling and disabling of each output
individually.
The ICS870S208 is characterized at full 3.3V and 2.5V, and mixed
3.3V/2.5V output operating supply modes. Guaranteed output and
part-to-part skew characteristics make the ICS870S208 ideal for
high performance, single ended applications.
Features
• Eight LVCMOS/LVTTL outputs, (2 banks of 4 outputs)
Each output has individual synchronous output enable
• Two selectable differential CLKx, nCLKx inputs
• Dual differential input pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
• Maximum output frequency: 250MHz
• Selectable 1 or 2 operation
• Glitchless output behavior during input switch
• Output skew: 120ps (maximum), 3.3V
• Bank skew: 65ps (maximum), 3.3V
• Supply modes:
Core/Output
3.3V/3.3V
2.5V/2.5V
3.3V/2.5V
• 0°C to 70°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Block Diagram
DIV_SELA ^Pulldown
CLK0 ^Pulldown
nCLK0 ^Pullup
0
÷1
0
CLK1 ^Pulldown
÷2
1
nCLK1 ^Pullup
1
CLK_SEL ^Pulldown
0
1
DIV_SELB ^Pulldown
QA0
OE_A0
QA1
OE_A1
QA2
OE_A2
QA3
OE_A3
QB0
OE_B0
QB1
OE_B1
QB2
OE_B2
QB3
OE_B3
Pin Assignment
32 31 30 29 28 27 26 25
DIV_SELB 1
24 OE_B3
CLK0 2
23 OE_B2
nCLK0 3
22 OE_B1
VDD 4
21 OE_B0
CLK_SEL 5
20 OE_A3
CLK1 6
19 OE_A2
nCLK1 7
18 OE_A1
DIV_SELA 8
17 OE_A0
9 10 11 12 13 14 15 16
ICS870S208
32-Lead VFQFN
5mm x 5mm x 0.9mm package body
3.15mm x 3.15mm EPad Size
K Package
Top View
ICS870S208BKLF REVISION A APRIL 3, 2013
1
©2013 Integrated Device Technology, Inc.