ICS870S208 Datasheet, PDF (5/20 Pages) Integrated Device Technology – Glitchless output behavior during input switch

ICS870S208 Data Sheet
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
Bad Input Clock
An internal timer monitors the state of both input clocks. If a clock is
stopped (stuck high or low for over approximately 200ns), its internal
input bad flag is set and the part will perform as depicted in the
following diagrams. If the clock is restored, the internal input bad
detector waits for 4 full clock periods before clearing the input bad
flag and returning to normal operation.
If the selected input clock goes bad (stuck high or low for over
approximately 200ns), an internal input bad flag is set. When the
input bad flag is set, the output goes low until the next valid clock
event. If the selected clock is restored, the input bad detector waits 4
full clock periods before clearing the flag and returning to normal
operation. If CLK_SEL is changed to select a valid input clock, the
output will stay low for one full period of the new input clock, then
return to normal operation.
CLK0
CLK1
CLK_SEL
Output
Input Bad
Detect, 200ns
Figure 1D. CLK_SEL with Bad Input Timing Diagram
If the selected input clock goes bad (stuck high or low for over
approximately 200ns), an internal input bad flag is set. When the
input bad flag is set, the output goes low until the next valid clock
CLK
CLK÷2
DIV_SEL
Output
Input Bad
Detect, 200ns
Figure 1E. DIV_SELx with Bad Input Timing Diagram
event. If DIV_SEL is changed, the output will transition from the
low state following the selected divide when a valid input clock is
restored.
If the input bad flag has been set (The input has been stuck high or
low for over approximately 200ns), and OEx is pulled low, the output
will immediately go to a High-Impedance state. If the clock is restored
while the OEx is low, the output will transition from the High-
Impedance to a low state to ensure a clean rising edge of the first
output clock when the Oex is pulled high again.
CLK
OE
Output
Input Bad
Detect, 200ns
Figure 1F. OEx with Bad Input Timing Diagram
ICS870S208BKLF REVISION A APRIL 3, 2013
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