ICS8536AG Datasheet, PDF (6/21 Pages) Integrated Device Technology – Low Skew, 1-to-6, Crystal LVCMOS Differential-to-3.3V, 2.5V LVPECL Fanout Buffer

ICS8536-01 Data Sheet
CRYSTAL/LVCMOS/DIFFERENTIAL-TO-LVPECL FANOUT BUFFER
TABLE 6A.
AC
CHARACTERISTICS,
V_CC =
3.3V±5%,
V=
EE
0V,
TA
=
0°C
TO
70°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CLK1/nCLK1
f
Output Frequency
OUT
CLK0
700
MHz
300
MHz
t_PD
tjit
tsk(o)
Propagation Delay, ^CLK1/nCLK1
NOTE1A, 1B
CLK0
1.7
2.5
ns
1.35
2.0
ns
Buffer Additive Phase Jitter, RMS; CLK1/nCLK1, 155.52MHz,
refer to Additive Phase Jitter
Integration Range:
0.19
ps
Section; NOTE 2
12kHz - 20MHz
Output Skew; NOTE 3, 5
55
ps
tsk(pp)
Part-to-Part Skew; NOTE 4, 5
450
ps
t_R / t_F
Output Rise/Fall Time
20% to 80%
200
CLK1/nCLK1
48
odc
Output Duty Cycle
CLK0
44
700
ps
52
%
56
%
MUX__ISOLATION MUX Isolation
NOTE 6A
NOTE 6B
ƒ= 150MHz
ƒ= 250MHz
-76
dB
-75
dB
All parameters measured at f_OUT ≤ 300MHz unless noted otherwise.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter
NOTE 1A: Measured from the differential input crossing point to the differential output crossing point.
NOTE 1B: Measured from V_CC/2 input crossing point to the differential output crossing point.
NOTE 2: Driving only one input clock.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6A: CLK0 (150MHz) sensitivity is measured with CLK_SEL[1:0] = 00.
NOTE 6B: CLK0 (250MHz) sensitivity is measured with CLK_SEL[1:0] = 1X.
TABLE 6B.
AC
CHARACTERISTICS,
V_CC =
2.5V±5%,
V
EE
=
0V,
TA
=
0°C
TO
70°C
Symbol
Parameter
Test Conditions
CLK1, nCLK1
f_MAX
Output Frequency
CLK0
t_PD
tjit
tsk(o)
Propagation Delay, ^{CLK1, nCLK1}
NOTE1A, 1B
CLK0
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section; NOTE 2
Output Skew; NOTE 3, 5
CLK1, nCLK1, 155.52MHz,
Integration Range:
12kHz - 20MHz
tsk(pp)
Part-to-Part Skew; NOTE 4, 5
t_R / t_F
odc
Output Rise/Fall Time
CLK1, nCLK1
Output Duty Cycle
CLK0
20% to 80%
MUX__ISOLATION MUX Isolation
For notes, see Table 6A above.
NOTE 6A
NOTE 6B
ƒ= 150MHz
ƒ= 250MHz
Minimum Typical Maximum Units
700
MHz
300
MHz
1.7
2.65
ns
1.4
2.05
ns
0.19
ps
55
ps
450
ps
200
700
ps
48
52
%
46
54
%
-76
dB
-75
dB
ICS8536AG-01 REVISION B AUGUST 17, 2012
6
©2012 Integrated Device Technology, Inc.