ICS8536AG Datasheet, PDF (15/21 Pages) Integrated Device Technology – Low Skew, 1-to-6, Crystal LVCMOS Differential-to-3.3V, 2.5V LVPECL Fanout Buffer

ICS8536-01 Data Sheet
CRYSTAL/LVCMOS/DIFFERENTIAL-TO-LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8536-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8536-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core) = V * I = 3.465V * 85mA = 294.525mW
MAX
CC_MAX
EE_MAX
• Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 6 * 30mW = 180mW
Total Power (3.465V, with all outputs switching) = 294.525mW + 180mW = 474.525mW
_MAX
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum
recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the
bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T = Ambient Temperature
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 84.6°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.475W * 84.6°C/W = 110.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θ FOR 24-PIN TSSOP, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
Multi-Layer PCB, JEDEC Standard Test Boards
0
84.6°C/W
1
80.3°C/W
2.5
78.1°C/W
ICS8536AG-01 REVISION B AUGUST 17, 2012
15
©2012 Integrated Device Technology, Inc.