ICS8536AG Datasheet, PDF (10/21 Pages) Integrated Device Technology – Low Skew, 1-to-6, Crystal LVCMOS Differential-to-3.3V, 2.5V LVPECL Fanout Buffer

ICS8536-01 Data Sheet
CRYSTAL/LVCMOS/DIFFERENTIAL-TO-LVPECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how a differential input can be wired to accept
single ended levels. The reference voltage V1 = Vcc/2 is generated
by the bias resistors R1 and R2. The bypass capacitor (C1) is
used to help filter noise on the DC bias. This bias circuit should be
located as close to the input pin as possible. The ratio of R1 and
R2 might need to be adjusted to position the VREF in the center of
the input voltage swing. For example, if the input clock swing is
2.5V and Vcc = 3.3V, R1 and R2 value should be adjusted to set V1
at 1.25V. The values below are for when both the single-ended
swing and Vcc are at the same voltage. This configuration requires
that the sum of the output impedance of the driver (Ro) and the
series resistance (Rs) equals the transmission line impedance. In
addition, matched termination at the input will attenuate the signal
in half. This can be done in one of two ways. First, R3 and R4 in
50 applications, R3 and R4 can be 100Ω. The values of the resistors
can be increased to reduce the loading for slower and weaker
LVCMOS driver. When using single ended signaling, the noise
rejection benefits of differential signaling are reduced. Even though
the differential input can handle full rail LVCMOS signaling, it is
recommended that the amplitude be reduced. The datasheet
specifies a lower differential amplitude, however this only applies
to differential signals. For single-ended applications, the swing can
be larger, however V_IL cannot be less than -0.3V and VIH cannot be
more than Vcc + 0.3V. Though some of the recommended
components might not be used, the pads should be placed in the
layout. They can be utilized for debugging purposes. The datasheet
specifications are characterized and guaranteed by using a
differential signal.
parallel should equal the transmission line impedance. For most
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
CRYSTAL INPUT INTERFACE
The ICS8536-01 has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 below
were determined using an 18pF parallel resonant crystal and
were chosen to minimize the ppm error.
X1
18pF Parallel Crystal
XTAL_IN
C1
22p
XTAL_OUT
C2
22p
FIGURE 2. CRYSTAL INPUt INTERFACE
ICS8536AG-01 REVISION B AUGUST 17, 2012
10
©2012 Integrated Device Technology, Inc.