810001-22_17 Datasheet, PDF (6/19 Pages) Integrated Device Technology – FemtoClock™ Dual VCXO Video PLL

810001-22 DATA SHEET
Table 3F. PLL Output Divider Function Table
Input
N1
N0
Operation
0 (default)
0 (default) Output divider N = 4.
0
1
Output divider N = 8.
1
0
Output divider N = 12.
1
1
Output divider N = 18.
Table 3G. PLL BYPASS Logic Function Table
Input
nBP1
nBP0
Operation
0
0
VCXO-PLL mode: The input reference frequency is multiplied by the VCXO-PLL. f_OUT = f_REF * M.
0
1
Test mode: The input reference frequency is divided by the output divider N and bypasses both PLLs.
f_OUT = f_REF ÷ N.
FemtoClock Mode: The input reference frequency is multiplied by the 2^nd PLL (FemtoClock, MF). The
1
0
1^st PLL (VCXO-PLL, M) is bypassed. This mode does not support jitter attenuatiion. f_OUT = f_REF * MF
÷ N.
1 (default)
1 (default)
Dual PLL Mode: both PLLs are cascaded for jitter attenuation and frequency multiplication.
f_OUT = f_REF * M * MF ÷ N.
FEMTOCLOCK™ DUAL VCXO VIDEO PLL
6
Rev A 8/14/15