810001-22_17 Datasheet, PDF (5/19 Pages) Integrated Device Technology – FemtoClock™ Dual VCXO Video PLL

810001-22 DATA SHEET
Table 3B. Output Frequency Table (Dual PLL Mode)
FemtoClock Look-up Table
f_VCXO
MF
N1
N0
0
0
0
0
0
1
0
1
0
0
27MHz
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
26.973MHz
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Output Frequency f_Q (MHz)
148.5000
74.2500
49.5000
33.0000
162.0000
81.0000
54.0000
36.0000
148.3515
74.1758
49.4505
32.9670
161.8382
80.9191
53.9461
35.9640
NOTE: Use the VCXO-PLL mode to achieve output frequencies of 27MHz or 26.973MHz. See Table 3G.
Table 3C. CLK_SEL Function Table
Input
CLK_SEL Operation
0 (default) Selects CLK0 as PLL reference input.
1
Selects CLK1 as PLL reference input.
Table 3D. MR Master Reset Function Table
Input
MR
Operation
0 (default) Normal operation, internal dividers and the output Q are enabled.
1
Internal dividers are reset. Q output is in logic low state (with OE = 1).
Table 3E. FemtoCLock PLL Feedback Divider Function Table
Input
MF
Operation
0 (default) Selects MF = 22. The 2nd stage PLL (FemtoClock. multiplies the output frequency of the VCXO-PLL by 22.
1
Selects MF = 24. The 2nd stage PLL (FemtoClock. multiplies the output frequency of the VCXO-PLL by 24.
Rev A 8/14/15
5
FEMTOCLOCK™ DUAL VCXO VIDEO PLL