810001-22_17 Datasheet, PDF (11/19 Pages) Integrated Device Technology – FemtoClock™ Dual VCXO Video PLL

Application Information
Recommendations for Unused Input Pins
Inputs:
CLK Inputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
810001-22 DATA SHEET
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 810001-22 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. V_DD, V_DDA, V_DDO and V_DDX should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic V_DD pin and also shows that V_DDA requires that an
additional 10 resistor along with a 10F bypass capacitor be
connected to the V_DDA pin.
VDD
V_DDX
3.3V
.01µF
10Ω
10Ω
.01µF 10µF
V_DDA
.01µF 10µF
Figure 1. Power Supply Filtering
Rev A 8/14/15
11
FEMTOCLOCK™ DUAL VCXO VIDEO PLL