810001-22_17 Datasheet, PDF (13/19 Pages) Integrated Device Technology – FemtoClock™ Dual VCXO Video PLL

810001-22 DATA SHEET
Schematic Example
Figure 3 shows an example of the 810001-22 application schematic.
In this example, the device is operated at V_DD = V_DDO = 3.3V. The
decoupling capacitors should be located as close as possible to the
power pin. The input is driven by a 3.3V LVPECL driver. An optional
3-pole filter can also be used for additional spur reduction. It is
recommended that the loop filter components be laid out for the
3-pole option. This will also allow the 2-pole filter to be used.
Logic Control Input Examples
Set Logic
VDD _{Input to}
'1'
RU1
1K
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
C1
SPARE
XTAL_OUT0
X1
3-pole loop filter example - (optional)
R1
LF
LF
VDD
Rs
150k
Cs
0.18uF
820k
Cp
0.68nF
C5
220pF
R2
10
C7
10u
C3
SPARE
VDDX
XTAL_IN0
C8
0.01u
U1
2-pole loop filter with Mid LBW Setting
Rs
150k
Cs
0.18uF
VDD
Cp
0.68nF
C9
0.1u
LF
LF
nPB0
GND
CLK_SEL
R4
5.6K
1
2
LF1
3 ^LF0
4
5
6
7
ISET
VDD
nPB0
GND
8 ^CLK_SEL
CLK1
VDD
Q1
Ro ~ 7 Ohm R9
Zo = 50 Ohm
43
Driv er_LVCMOS
CLK0
XTAL_IN1
X2
XTAL_OUT1
VDD
C2
SPARE
C4
SPARE
C6
0.1u
VDD = VDDO = 3.3V
N0
24
23
N1 ₂₂
nBP1
OE
GND
Q
21
20
19
18
VDDO ₁₇
VDDA
N0
N1
nBP1
OE
GND
VDDO
R3
VDDO
33
C10
0.1u
VDD
R5
VDDA
10
C11
C12
0.01u
10u
VDD
C13
0.1u
Zo = 50
Receiv er
Figure 3. 810001-22 Schematic Example
Rev A 8/14/15
13
FEMTOCLOCK™ DUAL VCXO VIDEO PLL