92HD91 Datasheet, PDF (51/298 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD91
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
3.5.2. SPDIF Timing
Parameter
SPDIF_OUT Frequency
SPDIF_OUT unit interval
SPDIF_OUT jitter
SPDIF_OUT rise time
SPDIF_OUT fall time
Definition
Symbol
highest rate of encoded signal
64 times the sample rate
1/(128 times the sample rate)
UI
SPDIF_OUT jitter
T_rise
T_fall
Table 24. SPDIF Timing
Min
2.8224
177.15
Typ
3.072
162.76
Max
12.288
40.69
4.43
15
15
Units
MHz
ns
ns
ns
ns
3.5.3. Digital Microphone Timing
Parameter
DMIC_CLK Frequency
DMIC_CLK Period
DMIC_CLK jitter
DMIC Data setup
DMIC Data hold
Definition
Symbol
Average DMIC_CLK frequency
Period of DMIC_CLK
Tdmic_cyc
DMIC_CLK jitter
Setup for the microphone data at both rising
and falling edges of DMIC_CLK
Tdmic_su
Hold for the microphone data at both rising and
falling edges of DMIC_CLK
Tdmic_h
Table 25. Digital Mic timing
Min
1.176
850.34
5
5
Typ
2.352
425.17
Max
4.704
212.59
5000
Units
MHz
ns
ps
ns
ns
3.5.4. GPIO Characteristics
Parameter
Definition
Symbol
Min
Typ
Max
Units
Input High Voltage¹
input level at or above which a 1 is reliably
recorded
Vih
0.6 x
VDD
V
Input Low Voltage¹
input level at or below which a 0 is reliably
recorded. VDD may be DVDD or AVDD
Vil
0.35 x
VDD
V
Output High Voltage
iout = 4mA
VDD may be DVDD or AVDD depending on pin
Voh
0.9 x
VDD
V
Output Low Voltage
iout = -4mA
VDD may be DVDD or AVDD depending on pin
Vol
0.1 x
VDD
V
Input rise/fall time
transition time between 10% and 90% of supply T_rise/T_fall
10
ns
Input/Tristate High
Leakage Current
Vin = VDD
VDD may be DVDD or AVDD depending on pin
(does not include pull-up or pull-down resistor if
present)
0.5
uA
Input/Tristate Low Leakage
Current
Vin = 0
VDD may be DVDD or AVDD depending on pin
(does not include pull-up or pull-down resistor if
present)
-50
uA
Table 26. GPIO Characteristics
1.High peak currents during dynamic switching of the Class-D PWM Outputs can result in Ground Rail Bounce. The amount of
Ground Bounce should be kept below 0.35 x VDD for all Inputs, including internal logic which is tied to DVDD_CORE.
IDT CONFIDENTIAL
51
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V 1.2 1/12
92HD91