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92HD91 Datasheet, PDF (25/298 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM
92HD91
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
HP SD
0
0
0
0
0
0
0
0
1
1
HP SD
MODE
0
0
0
0
1
1
1
1
0
1
HP SD INV
0
0
1
1
0
0
1
1
NA
NA
EAPD Pin
State
0
1
0
1
0
1
0
1
NA
NA
Headphone Amp State
Amplifier is mute (default1)
Amplifier is active
Amplifier is active
Amplifier is mute
Amplifier is in a low power state
Amplifier is active
Amplifier is active
Amplifier is in a low power state
Amplifier follows pin/function group power state and will mute when disabled
Amplifier follows pin/function group power state and will enter a low power
state when disabled
Table 12. Headphone Amp Enable Configuration
1. EAPD bit is set to one by default but the EAPD state is 0 after power-on reset because the function group is not in D0. The
state after a single or double function group reset will be compliant with HDA015-B.
Port E Headphone Amp Enable Configuration Bits
SD (EAPD Pin or power setting)
SD INV
SD MODE (power down or mute)
Normal Mode
Aux Mode
Not supported1
Not supported1
supported2
Not supported1
Table 13. Port E Headphone Amp Enable Configuration support by part and mode
1. Port E not headphone capable on the 92HD94
2. Port E is typically connected to the dock headphone port. In Aux mode, EAPD will mute the record path on the 92HD94.
Analog
BEEP
enabled
0
1
EAPD Pin value1
Description
Forced to low when in D2
or D3
Forced low in D2 or D3
unless port is enabled as
output
Follows description in HD Audio spec. External amplifier is shut down when pin or function
group power state is D2 or D3 independent of value in EAPD bit.
Power state is ignored if port is enabled as output and port EAPD=1 to allow PC_Beep
support in D2 and D3
Table 14. EAPD Analog PC_Beep behavior
1. When pin is enabled as Open Drain or CMOS output.
AFG
Power
State
D0-D3
D0
D1
D2
RESET#
Asserted (Low)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
Analog Port Power
PC_BEEP
State
Pin Behavior
-
-
-
Disabled
-
Active low immediately after power on, otherwise the previous
state is retained across FG and link reset events
-
Active - Pin reflects EAPD bit unless held low by external source.
D0-D1 Active - Pin reflects EAPD bit unless held low by external source.
D0-D2
Pin forced low to disable external amp
Table 15. EAPD Behavior
IDT™ CONFIDENTIAL
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©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
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92HD91