92HD91 Datasheet, PDF (287/298 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD91
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
7.29.1.23. LDO LEVEL CONTROL Register
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause NOT generate a reset.
Register Address
verb F9B/79B
Bit
Label
Type Default
Description
7:3 Reserved
RO 0x0
RESERVED
2
Lv_QUAD_BIAS RW 0
1:0 Lv_reg_cntrl_bit RW 0x0
Two bits are defined to program the output of the 1.8V LDO
00 = normal operation (3.3V in to 1.8V out)
01 = 1.8V*1.1 = 1.98V
10 = 1.8V*0.9 = 1.62V
11 = power down LDO/bypass. When disabled, the
DVDD_Core pin must be supplied with a nominal 1.8V from
an external source.
7.29.1.24. EQRAM
The EQ RAM is a 52 x 48-bit SRAM that contains the EQ coefficients
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only OR
when a BIST is run under certain conditions, contact IDT for more information. Writing to NID22h
verb 77F will cause NOT generate a reset..
Address
EQRAM
Bits
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
Channel RIGHT Coefficients (24bit)
[47:24]
Channel LEFT Coefficients (24bit)
[23:00]
based on 44.1Khz sample rate
EQ_COEF_F0_B0
EQ_COEF_F0_B0
EQ_COEF_F0_B1
EQ_COEF_F0_B1
EQ_COEF_F0_B2
EQ_COEF_F0_B2
EQ_COEF_F0_A1
EQ_COEF_F0_A1
EQ_COEF_F0_A2
EQ_COEF_F0_A2
EQ_COEF_F1_B0
EQ_COEF_F1_B0
EQ_COEF_F1_B1
EQ_COEF_F1_B1
EQ_COEF_F1_B2
EQ_COEF_F1_B2
EQ_COEF_F1_A1
EQ_COEF_F1_A1
EQ_COEF_F1_A2
EQ_COEF_F1_A2
EQ_COEF_F2_B0
EQ_COEF_F2_B0
EQ_COEF_F2_B1
EQ_COEF_F2_B1
EQ_COEF_F2_B2
EQ_COEF_F2_B2
EQ_COEF_F2_A1
EQ_COEF_F2_A1
EQ_COEF_F2_A2
EQ_COEF_F2_A2
EQ_COEF_F3_B0
EQ_COEF_F3_B0
EQ_COEF_F3_B1
EQ_COEF_F3_B1
EQ_COEF_F3_B2
EQ_COEF_F3_B2
EQ_COEF_F3_A1
EQ_COEF_F3_A1
EQ_COEF_F3_A2
EQ_COEF_F3_A2
EQ_COEF_F4_B0
EQ_COEF_F4_B0
IDT CONFIDENTIAL
287
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
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92HD91