92HD91 Datasheet, PDF (28/298 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD91
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
The codec supports the following digital microphone configurations:
Digital
Mics
0
Data Sample
N/A
1
Single Edge
2
Double Edge on
either DMIC_0 or 1
Double Edge on
3
one DMIC pin and
Single Edge on the
second DMIC pin.
4
Double Edge
ADC
Conn.
N/A
0, or 1
0, or 1
0, or 1
0, or 1
Notes
No Digital Microphones
Available on either DMIC_0 or DMIC_1
When using a microphone that supports multiplexed operation (2-mics can share a
common data line), configure the microphone for “Left” and select mono operation using
the vendor specific verb.
“Left” D-mic data is used for ADC left and right channels.
Available on either DMIC_0 or DMIC_1, External logic required to support sampling on a
single Digital Mic pin channel on rising edge and second Digital Mic right channel on
falling edge of DMIC_CLK for those digital microphones that don’t support alternative
clock edge (multiplexed output) capability.
Requires both DMIC_0 and DMIC_1, External logic required to support sampling on a
single Digital Mic pin channel on rising edge and second Digital Mic right channel on
falling edge of DMIC_CLK for those digital microphones that don’t support alternative
clock edge (multiplexed output) capability. Two ADC units are required to support this
configuration
Connected to DMIC_0 and DMIC_1, External logic required to support sampling on a
single Digital Mic pin channel on rising edge and second Digital Mic right channel on
falling edge of DMIC_CLK for those digital microphones that don’t support alternative
clock edge capability. Two ADC units are required to support this configuration
Table 16. Valid Digital Mic Configurations
Power State
DMIC Widget
Enabled?
DMIC_CLK
Output
D0
Yes
Clock Capable
D1-D3
D0-D3
D4
D5
Yes
Clock Disabled
No
Clock Disabled
-
Clock Disabled
-
Clock Disabled
DMIC_0,1
Input Capable
Input Disabled
Input Disabled
Input Disabled
Input Disabled
Notes
DMIC_CLK Output is Enabled when either DMIC_0 or DMIC_1
Input Widget is Enabled. Otherwise, the DMIC_CLK remains Low
DMIC_CLK is HIGH-Z with Weak Pull-down
DMIC_CLK is HIGH-Z with Weak Pull-down
DMIC_CLK is HIGH-Z with Weak Pull-down
DMIC_CLK is HIGH-Z with Weak Pull-down
Table 17. DMIC_CLK and DMIC_0,1 Operation During Power States
IDT™ CONFIDENTIAL
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©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
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92HD91