ICS844S0258-07 Datasheet, PDF (4/21 Pages) Integrated Device Technology – Output enable signal for three LVDS outputs

ICS844S0258-07 Data Sheet
FEMTOCLOCK^® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 4C. LVDS DC Characteristics, V_DD = V_{DDO_LVDS} = 3.3V ± 5%, T_A = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
V_OD
V_OD
V_OS
V_OS
Differential Output Voltage
V_OD Magnitude Change
Offset Voltage
V_OS Magnitude Change
300
1.15
Typical
400
1.30
Maximum
525
50
1.45
50
Units
mV
mV
V
mV
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance
Shunt Capacitance
Test Conditions
Minimum
Typical
Fundamental
25
Maximum
50
7
Units
MHz

pF
Table 6. AC Characteristics, V_DD = V_{DDO_LVCMOS} = V_{DDO_LVDS} = 3.3V ± 5%, T_A = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
f_out
tjit(Ø)
Output Frequency
RMS Phase
Noise Jitter;
NOTE 1
LVDS
LVCMOS
125MHz, Integration Range:
1.857MHz - 20MHz
125MHz, Integration Range:
1.857MHz - 20MHz
125
0.278
0.284
Phase Jitter
125MHz, (1.2MHz – 21.9MHz),
t_j
Peak-to-Peak;
Evaluation Band: 0Hz - Nyquist
8.57
NOTE 2
(clock frequency/2)
t_{REFCLK_HF_RMS}
Phase Jitter RMS; NOTE
3
125MHz,
25MHz crystal input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
0.86
t_{REFCLK_LF_RMS}
Phase Jitter RMS; NOTE
3
125MHz,
25MHz crystal input
Low Band: 10kHz - 1.5MHz
0.12
t_R / t_F
Output
Rise/Fall
Q[0:6]:
nQ[0:6]
30% to 70%, 15pF Load
70
Time
Q7
20% to 80%
400
odc
Output Duty Cycle
48
odc
Output Duty Cycle,
Bypass Mode
45
Maximum
Units
MHz
ps
ps
ps
ps
ps
650
ps
900
ps
52
%
55
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Refer to Phase Noise Plots.
NOTE 2: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 10⁶ clock periods. See IDT Application Note PCI Express Reference Clock Requirements and also
the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.
NOTE 3: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for t_{REFCLK_HF_RMS} (High
Band) and 3.0ps RMS for t_{REFCLK_LF_RMS} (Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also the
PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.
ICS844S0258CK-07 REVISION A DECEMBER 2, 2013
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