ICS844S0258-07 Datasheet, PDF (1/21 Pages) Integrated Device Technology – Output enable signal for three LVDS outputs

FemtoClock^® Crystal/LVCMOS-to-
LVDS/LVCMOS Frequency Synthesizer
ICS844S0258-07
DATASHEET
General Description
The ICS844S0258-07 is an eight output synthesizer optimized to
generate Gigabit and 10 Gigabit Ethernet clocks. Using a 25MHz,
18pF parallel resonant crystal, the device will generate 125MHz
clocks with mixed LVDS and LVCMOS/ LVTTL output levels.
ICS844S0258-07 uses IDT’s 3^rd generation low phase noise VCO
technology and can achieve <1ps typical RMS phase jitter, easily
meeting Ethernet jitter requirements. ICS844S0258-07 is packaged
in a small, 32-pin VFQFN package that is optimum for applications
with space limitations.
Features
• Seven LVDS differential output at 125MHz
One LVCMOS/LVTTL single-ended outputs at 125MHz
• Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input and PLL bypass from a single select pin
• Output enable signal for three LVDS outputs
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.857MHz - 20MHz): 0.278ps (typical)
• PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Pin Assignment
nPLL_BYPASS ^Pullup
Block Diagram
REF_CLK ^Pulldown
0
32 31 30 29 28 27 26 25
Q0 1
24 GND
nQ0 2
23 Q7
XTAL_IN
25MHz
OSC
1
GND 3
22 VDDO_LVCMOS
XTAL_OUT
Q1 4
21 ^nQ6
nQ1 5
20 Q6
VDDO_LVDS 6
19 VDDO_LVDS
Q2 7
18 nQ5
nQ2 8
17 Q5
9 10 11 12 13 14 15 16
Phase
Detector
VCO
÷25
0
÷5
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
ICS844S0258-07
Q5
32-Lead VFQFN
nQ5
5mm x 5mm x 0.925mm
Q6
package body
nQ6
K Package
Top View
OE ^Pullup
Q7
ICS844S0258CK-07 REVISION A DECEMBER 2, 2013
1
©2013 Integrated Device Technology, Inc.