ICS844S0258-07 Datasheet, PDF (18/21 Pages) Integrated Device Technology – Output enable signal for three LVDS outputs

ICS844S0258-07 Data Sheet
FEMTOCLOCK^® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
Ind exArea
N
To p View
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
S eating Plan e
A1
A_An_nv_vi_il_l
Si_Sn_ig_ngu_ula_lati_to_ion_n
OR
A3 ^L
E 2 _E2
2
(N -1)x e
(R ef.)
(Ref.)
N &N
Even
N
e (Ty p.)
2 _{If N & N}
1 ^{are Even}
2
(N -1)x e
(Re f.)
A
0. 08 C
e
(Ref.)
N &N
Odd
C
D2
2
D2
b
Th er mal
Ba se
Bottom View w/Type A ID
Bottom View w/Type C ID
2
2
1
1
CHAMFER
4
N N-1
RADIUS
4
N N-1
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
Table 9. Package Dimensions
Symbol
N
A
A1
A3
b
N_D & N_E
D&E
D2 & E2
e
L
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Minimum
Nominal
32
0.80
0
0.25 Ref.
0.18
0.25
5.00 Basic
3.0
0.50 Basic
0.30
0.40
Maximum
1.00
0.05
0.30
8
3.3
0.50
Reference Document: JEDEC Publication 95, MO-220
ICS844S0258CK-07 REVISION A DECEMBER 2, 2013
The following package mechanical drawing is a generic drawing that
applies to any pin count VFQFN package. This drawing is not
intended to convey the actual pin count or pin layout of this device.
The pin count and pinout are shown on the front page. The package
dimensions are in Table 9.
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©2013 Integrated Device Technology, Inc.