ICS844S0258-07 Datasheet, PDF (13/21 Pages) Integrated Device Technology – Output enable signal for three LVDS outputs

ICS844S0258-07 Data Sheet
FEMTOCLOCK^® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Schematic Example
Figure 6 shows an example of ICS844S0258-07 application
schematic. In this example, the device is operated at
V_DD = V_{DDO_LVDS} = V_{DDO_LVCMOS} = 3.3V. The 18pF parallel resonant
25MHz crystal is used. The C1 = 22pF and C2 = 22pF are
recommended for frequency accuracy. For different board layouts,
the C1 and C2 may be slightly adjusted for optimizing frequency
accuracy. Two examples of LVDS for receiver without built-in
termination and one example of LVCMOS are shown in this
schematic.
VDD
Q1
R1 ₃₃
Zo = 50
LVCMOS_Driv er
C1
22pF
X1
C2
22pF
R1 ₁₀
C3
0.01uF
XTAL_IN
18pF
25MHz
XTAL_OUT
VDDA
C5
10uF
REF_CLK
VDD
VDD
C4
0.1uF
VDDO
Logic Input Pin Examples
Q0
nQ0
VDDO
1
2
3
4
5
6
7
8
Q0
nQ0
GND
Q1
nQ1
VDDO_LVDS
Q2
nQ2
GND
Q7
VDDO_LVCMOS
nQ6
Q6
VDDO_LVDS
nQ5
Q5
24
23
22
21
20
19
18
17
Q7
nQ6
Q6
VDD
Set Logic
Input to
'1'
RU1
1K
VDD
Set Logic
Input to
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
U1
VDDO
(U1:6) VDDO (U1:12) (U1:19)
(U1:22)
C7
C8
C9
C10
0.1uF
0.1uF
0.1uF
0.1uF
Figure 6. ICS844S0258-07 Schematic Example
Zo = 50 Ohm
Q0
+
R2
Zo = 50 Ohm 100
nQ0
-
VDD=3.3V
VDDO_LVDS=3.3V
VDDO_LVCMOS=3.3V
Zo = 50 Ohm
Q6
R3
50
+
C6
0.1uF
-
R4
Zo = 50 Ohm
50
nQ6
Alternate
LVDS
Termination
R5
30 Zo = 50 Ohm
Q7
LVCMOS
ICS844S0258CK-07 REVISION A DECEMBER 2, 2013
13
©2013 Integrated Device Technology, Inc.