ICS844S0258-07 Datasheet, PDF (16/21 Pages) Integrated Device Technology – Output enable signal for three LVDS outputs

ICS844S0258-07 Data Sheet
FEMTOCLOCK^® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS844S0258-07.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS44S0258-07 is the sum of the core power plus the analog plus the power dissipated in the load(s).
The following is the power dissipation for V_DD = 3.3V + 5% = 3.465V, which gives worst case results.
Core and LVDS Output Power Dissipation
• Power (core, LVDS) = V_{DD_MAX} * (I_DD + I_{DDO_LVDS} + I_DDA) = 3.465V * (80mA + 120mA + 20mA) = 762.3mW
LVCMOS Output Power Dissipation
• Output Impedance R_OUT Power Dissipation due to Loading 50 to V_DDO/2
Output Current I_OUT = V_{DDO_MAX} / [2 * (50 + R_OUT)] = 3.465V / [2 * (50 + 20)] = 24.75mA
• Power Dissipation on the R_OUT per LVCMOS output
Power (R_OUT) = R_OUT * (I_OUT)² = 20 * (24.75mA)² = 12.25mW per output
• Dynamic Power Dissipation at 125MHz
Power (125MHz) = C_PD * Frequency * (V_DDO)² = 12pF * 125MHz * (3.465V)² = 18.01mW per output
Total Power Dissipation
• Total Power
= Power (core, LVDS) + Power (R_OUT) + Power (125MHz)
= 762.3mW + 12.25mW + 18.01mW
= 792.56mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = _JA * Pd_total + T_A
Tj = Junction Temperature
_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 39.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.793W * 39.5°C/W = 101.3°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance _JA for 32 Lead VFQFN, Forced Convection
_JA Vs. Air Flow
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
39.5°C/W
1
34.5°C/W
2.5
31.0°C/W
ICS844S0258CK-07 REVISION A DECEMBER 2, 2013
16
©2013 Integrated Device Technology, Inc.