ICS844S0258-07 Datasheet, PDF (2/21 Pages) Integrated Device Technology – Output enable signal for three LVDS outputs

ICS844S0258-07 Data Sheet
FEMTOCLOCK^® CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1, 2
3, 9, 15,
24, 28, 32
4, 5
Name
Q0, nQ0
GND
Q1, nQ1
Type
Output
Power
Output
6, 12, 19
7, 8
10, 11
13, 14
V_{DDO_LVDS}
Q2, nQ2
Q3, nQ3
Q4, nQ4
Power
Output
Output
Output
16
OE
Input
Pullup
17, 18
20, 21
22
23
25
26
27
29
30,31
Q5, nQ5
Q6, nQ6
V_{DDO_LVCMOS}
Q7
V_DD
nPLL_BYPAS
S
V_DDA
REF_CLK
XTAL_IN,
XTAL_OUT
Output
Output
Power
Output
Power
Input
Power
Input
Input
Pullup
Pulldown
Description
Differential clock outputs. LVDS interface levels.
Power supply ground.
Differential clock outputs. LVDS interface levels.
Output supply pins for differential LVDS outputs.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Output enable pin for Q[4:6]/nQ[4:6] outputs. If connected to HIGH or left
open, enables the outputs. When connected to LOW or GND, disables the
outputs to high-impedance state. LVCMOS/LVTTL interface levels.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Output supply pin for single-ended output.
Single-ended clock output. LVCMOS/LVTTL levels.
Core supply pin.
Input select and PLL bypass control pin. See Table 3.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Single-ended reference clock input. Only selected in nPLL_BYPASS
mode. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_OUT is the output, XTAL_IN is the input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
Input Capacitance
C_PD
Power Dissipation
Capacitance
Q7
R_PULLUP
R_PULLDOWN
R_OUT
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance Q7
Test Conditions
V_DD, V_{DDO_LVCMOS} = 3.465V
Minimum
Typical
2
12
51
51
20
Maximum
Units
pF
pF
k
k

Function Table
Table 3. PLL Bypass and Input Select Function Table
Inputs
nPLL_BYPASS
PLL Bypass
Input Selected
0
PLL Bypassed
REF_CLK
1
PLL Enabled
XTAL_IN/XTAL_OUT
ICS844S0258CK-07 REVISION A DECEMBER 2, 2013
2
©2013 Integrated Device Technology, Inc.