92HD81 Datasheet, PDF (32/279 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD81
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
1KHz, or 2KHz. The high pass filter is enabled by default with a cut-off
frequency of 300Hz. The filter may be bypassed using the associated verb (processing state verb).
The filter is implemented in digital before the Digital to Analog converter. There are 2 major conse-
quences to implementing the filter in the digital domain:
1. All ports connected to the DAC will be affected by the high-pass filer when it is enabled.
2. Analog paths (such as when the microphone input is routed through the mixer to the BTL ampli-
fier) are not affected.
Like the other analog inputs, PC_Beep is not affected by the digital high-pass filter. To ensure that
the speakers attached to the BTL amplifier are not harmed by low frequency audio entering the
PC_Beep input, an external filter must be implemented. Fortunately, it is common practice to imple-
ment an attenuation circuit and DC blocking capacitor at the PC_Beep input. This attenuator/filter is
easily adjusted to restrict low frequency audio. The easiest approach is to reduce the value of the
DC blocking capacitor but other approaches are equally effective.
2.20. GPIO
2.20.1. GPIO Pin mapping and shared functions
GPIO Pin
#
0 46
12
24
Supply SPDIF SPDIF GPI/O GPI GP VrefOut DMIC VOL Pull
In
Out
O
Up
DVDD
YES YES
IN
DVDD
YES
CLK
DVDD
YES
IN
Pull
Down
50K
50K
50K
2.20.2. SPDIF/Digital Microphone/GPIO Selection
3 functions are available on the DMIC_1/GPIO0/SPDIFOUT1 pin (pin 46). To determine which func-
tion is enabled, the order of precedence is followed:
3. If the GPIOs are enabled, they override both SPDIF_OUT and Digital Mics
4. If the GPIOs are not enabled through the AFG, then at reset, the pin is pulled low by an internal
pull-down resistor.
5. If the port is enabled as an input, the digital microphones will be used.
6. If the port is enabled as an output, the SPDIF output will be used.
7. In the event that the port is enabled as an input and an output, the port will be an output and the
Digital Mic path will be mute.
2.20.3. Digital Microphone/GPIO Selection
2 functions are available on the DMIC_CLK/GPIO1 (pin 2) and the DMIC_0/GPIO2 (pin 4) pins. To
determine which function is enabled, the order of precedence is followed:
1. If GPIOs are not enabled through the AFG, then at reset, pins 2 and 4 are pulled low by an inter-
nal pull-down resistor.
2. If the GPIO 1 is enabled, the 2 DMIC pins become mute (unless programmed for GPIO or SPDIF
use) and pin 2 becomes an internal pull-down.If GPIO2 is enabled through the AFG, pin 4
becomes a GPIO and is pulled low by an internal pull-down resistor.
3. If the port is enabled as an input, the digital microphones will be used.
IDT CONFIDENTIAL
32
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V 0.995 01/11
92HD81