92HD81 Datasheet, PDF (14/279 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD81
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
When the HD Audio bus is in a low power state (reset asserted and clock stopped) the CODEC will
generate a Power State Change Request when a change in port connectivity is sensed and then
generate an unsolicited response after the HD Audio link has been brought out of a low power state
and the device has been enumerated. Per HDA015-B, this will take less than 10mS.
The following table summarizes the proper resistor tolerances for different analog supply voltages.
AVdd Nominal
Voltage (+/- 5%)
4.75V
Resistor Tolerance
Pull-Up
1%
Resistor Tolerance
SENSE_A/B
1%
Resistor
39.2K
20.0K
10.0K
5.11K
2.49K
SENSE_A
PORT A (HP0)
PORT B (HP1)
PORT C
SPDIFOUT0
Pull-up to AVDD
SENSE_B
PORT E
PORT F
DMIC0
SPDIFOUT1
(DMIC1)
Pull-up to AVDD
See reference design for more information on Jack Detect implementation.
2.1.4. SPDIF Output
Both SPDIF Outputs can operate at 44.1kHz, 48kHz, 88.2kHz, 96kHz and 192KHz as defined in the
Intel High Definition Audio Specification with resolutions up to 24 bits. This insures compatibility with
all consumer audio gear and allows for convenient integration into home theater systems and media
center PCs.
Per the HDA015-B ECR, the SPDIF outputs support the ability to provide clocking information even
when no stream is selected for the converter, or when in a low power state. Also, as stated in the
ECR, the SPDIF output ports support port presence detect.
AFG Power
State
SPDIF Outputs are outlined in tables below.
RESET#
Output
Enable
Converter
Dig
Enable
Stream
ID
Keep Alive
Enable
D0-D3
Asserted (Low) -
-
-
-
Table 3. SPDIF OUT 0 Behavior
Pin Behavior
Hi-Z (internal pull-down
enabled) immediately after
power on, otherwise the
previous state is retained.
IDT CONFIDENTIAL
14
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V 0.995 01/11
92HD81