ICS9UMS9610CKLFT Datasheet, PDF (3/20 Pages) Integrated Device Technology – PC MAIN CLOCK

ICS9UMS9610
PC MAIN CLOCK
Advance Information
Pin Description (continued)
PIN #
PIN NAME
25 GNDSRC
26 SRCC0_LPR
27 SRCT0_LPR
28 *CR#1_1.5
29 VDDCORE_1.5
30 VDDIO_1.5
31 SRCC1_LPR
32 SRCT1_LPR
33 GNDSRC
34 SRCC2_LPR
35 SRCT2_LPR
36 *CR#2_1.5
37 FSB_L_1.5
38 CPUC2_LPR
39 CPUT2_LPR
40 GNDCPU
41 VDDIO_1.5
42 VDDCORE_1.5
43 CPUC1_LPR
44 CPUT1_LPR
45 GNDCPU
46 VDDIO_1.5
47 CPUC0_LPR
48 CPUT0_LPR
TYPE
DESCRIPTION
GND Ground pin for the SRC outputs
OUT
Complementary clock of differential 0.8V push-pull SRC output with
integrated 33ohm series resistor. No 50ohm resistor to GND needed.
OUT ^{True clock of differential 0.8V push-pull SRC output with integrated 33ohm}
series resistor. No 50ohm resistor to GND needed.
IN 1.5V Clock request for SRC1, 0 = enable, 1 = disable
PWR 1.5V power for the PLL core
PWR Power supply for low power differential outputs, nominal 1.5V.
Complementary clock of differential 0.8V push-pull SRC output with
OUT _{integrated 33ohm series resistor. No 50ohm resistor to GND needed.}
OUT
True clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
GND Ground pin for the SRC outputs
OUT
Complementary clock of differential 0.8V push-pull SRC output with
integrated 33ohm series resistor. No 50ohm resistor to GND needed.
OUT ^{True clock of differential 0.8V push-pull SRC output with integrated 33ohm}
series resistor. No 50ohm resistor to GND needed.
IN 1.5V Clock request for SRC2, 0 = enable, 1 = disable
IN ^{Low threshold input for CPU frequency selection. Refer to input electrical}
characteristics for Vil_FS and Vih_FS values. 1.5V Max input voltage.
Complementary clock of differential pair 0.8V push-pull CPU outputs with
OUT _{integrated 33ohm series resistor. No 50 ohm resistor to GND needed.}
OUT
True clock of differential pair 0.8V push-pull CPU outputs with integrated
33ohm series resistor. No 50 ohm resistor to GND needed.
GND Ground pin for the CPU outputs
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR 1.5V power for the PLL core
OUT
Complementary clock of differential pair 0.8V push-pull CPU outputs with
integrated 33ohm series resistor. No 50 ohm resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs with integrated
OUT _{33ohm series resistor. No 50 ohm resistor to GND needed.}
GND Ground pin for the CPU outputs
PWR Power supply for low power differential outputs, nominal 1.5V.
OUT ^{Complementary clock of differential pair 0.8V push-pull CPU outputs with}
integrated 33ohm series resistor. No 50 ohm resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs with integrated
OUT _{33ohm series resistor. No 50 ohm resistor to GND needed.}
Logic Level
(V)
0
0.8
0.8
1.5
1.5
1.5
0.8
0.8
0
0.8
0.8
1.5
1.5
0.8
0.8
0
1.5
1.5
0.8
0.8
0
1.5
0.8
0.8
Input Level
Tolerance (V)
N/A
N/A
N/A
1.5
1.5
1.5
N/A
N/A
N/A
N/A
N/A
1.5
1.5
N/A
N/A
N/A
1.5
1.5
N/A
N/A
N/A
1.5
N/A
N/A
IDT^TM/ICST^M PC MAIN CLOCK
3
1336—07/21/08