ICS9UMS9610CKLFT Datasheet, PDF (2/20 Pages) Integrated Device Technology – PC MAIN CLOCK

ICS9UMS9610
PC MAIN CLOCK
Advance Information
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1 CPU_STOP#_3.3
IN This active-low input stops all CPU clocks that are set to be stoppable.
This level sensitive strobe determines when latch inputs are valid and are
2 CLKPWRGD#/PD_3.3 IN ready to be sampled. When high, this asynchronous input places the
device into the power down state.
3 X2
OUT Crystal output, Nominally 14.318MHz
4 X1
IN Crystal input, Nominally 14.318MHz.
5 VDDREF_3.3
PWR Power pin for the XTAL and REF clocks, nominal 3.3V
6 REF_3.3_2x
OUT 3.3V 14.318 MHz reference clock. Default 2 load drive strength
7 GNDREF
GND Ground pin for the REF outputs.
8 VDDCORE_1.5
PWR 1.5V power for the PLL core
9 FSC_L_1.5
IN ^{Low threshold input for CPU frequency selection. Refer to input electrical}
characteristics for Vil_FS and Vih_FS values. 1.5V Max input voltage.
TEST_MODE is a real time input to select between Hi-Z and REF/N divider
10 TEST_MODE_1.5
IN mode while in test mode. Refer to Test Clarification Table. Max input
voltage is 1.5V.
Logic Level
(V)
3.3
3.3
N/A
1.5
3.3
3.3
0
1.5
1.5
1.5
11 TEST_SEL_1.5
TEST_SEL: latched input to select TEST MODE. Max input voltage is 1.5V
IN 1 = All outputs are tri-stated for test
1.5
0 = All outputs behave normally.
12 SCLK_3.3
13 SDATA_3.3
14 VDDCORE_1.5
15 VDDIO_1.5
16 DOT96C_LPR
17 DOT96T_LPR
18 GNDDOT
19 GNDLCD
20 LCD100C_LPR
21 LCD100T_LPR
22 VDDIO_1.5
23 VDDCORE_1.5
24 *CR#0_1.5
IN Clock pin of SMBus circuitry, 3.3V tolerant.
3.3
I/O Data pin for SMBus circuitry, 3.3V tolerant.
3.3
PWR 1.5V power for the PLL core
1.5
PWR Power supply for low power differential outputs, nominal 1.5V.
1.5
Complement clock of low power differential pair for 96.00MHz DOT clock.
OUT _{No 50ohm resistor to GND needed. No Rs needed.}
0.8
OUT
True clock of low power differential pair for 96.00MHz DOT clock. No
50ohm resistor to GND needed. No Rs needed.
0.8
GND Ground pin for DOT clock output
0
GND Ground pin for LCD clock output
0
Complement clock of low power differential pair for LCD100 SS clock. No
OUT _{50ohm resistor to GND needed. No Rs needed.}
0.8
OUT
True clock of low power differential pair for LCD100 SS clock. No 50ohm
resistor to GND needed. No Rs needed.
0.8
PWR Power supply for low power differential outputs, nominal 1.5V.
1.5
PWR 1.5V power for the PLL core
1.5
IN 1.5V Clock request for SRC0, 0 = enable, 1 = disable
1.5
Input Level
Tolerance (V)
3.3
3.3
N/A
1.5
3.3
N/A
N/A
1.5
1.5
3.3
3.3
3.3
3.3
1.5
1.5
N/A
N/A
N/A
N/A
N/A
N/A
1.5
1.5
1.5
IDT^TM/ICST^M PC MAIN CLOCK
2
1336—07/21/08