ICS9UMS9610CKLFT Datasheet, PDF (13/20 Pages) Integrated Device Technology – PC MAIN CLOCK

ICS9UMS9610
PC MAIN CLOCK
Advance Information
Byte
Bit(s)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
8 LCD100 PLL M/N Register
Pin #
Name
LCD100 N Div8
LCD100 N Div9
LCD100 M Div5
LCD100 M Div4
LCD100 M Div3
LCD100 M Div2
LCD100 M Div1
LCD100 M Div0
Control Function
N Divider Prog bit 8
N Divider Prog bit 9
M Divider Programming
bit (5:0)
Type
0
1
RW
RW The decimal representation of M
RW and N Divider in Byte 8 and 9 will
RW
configure the DOT VCO
RW frequency. VCO Frequency =
RW
14.318 x [NDiv(11:0)] /
RW
[MDiv(5:0)]
RW
Default
X
X
X
X
X
X
X
X
Byte
Bit(s)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9 LCD100 PLL M/N Register
Pin #
Name
Control Function
LCD100 N Div7
LCD100 N Div6
LCD100 N Div5
LCD100 N Div4 N Divider Programming Byte9 bit(7:0) and
LCD100 N Div3
Byte8 bit(7:6)
LCD100 N Div2
LCD100 N Div1
LCD100 N Div0
Type
0
1
RW
RW The decimal representation of M
RW and N Divider in Byte 8 and 9 will
RW
configure the DOT VCO
RW frequency. VCO Frequency =
RW
14.318 x [NDiv(11:0)] /
RW
[MDiv(5:0)]
RW
Default
X
X
X
X
X
X
X
X
Byte
Bit(s)
7
6
5
4
3
2
1
0
10 Status Readback Register
Pin #
Name
Description
37
FSB
Frequency Select B
9
FSC
Frequency Select C
24 CR0# Readbk
Real time CR0# State Indicator
28 CR1# Readbk
Real time CR1# State Indicator
36 CR2# Readbk
Real time CR2# State Indicator
Reserved
Reserved
Reserved
Type
R
R
R
R
R
0
1
See Table 1: CPU Frequency
Select Table
CR0# is Low CR0# is High
CR1# is Low CR1# is High
CR2# is Low CR2# is High
Default
Latch
Latch
X
X
X
0
0
0
Byte
Bit(s)
7
6
5
4
3
2
1
0
11 Revision ID/Vendor ID Register
Pin #
Name
Rev Code Bit 3
Rev Code Bit 2
Rev Code Bit 1
Rev Code Bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
Description
Revision ID
Vendor ID
Type
R
R
R
R
R
R
R
R
0
1
Vendor specific
Default
X
X
X
X
0
0
0
1
IDT^TM/ICST^M PC MAIN CLOCK
13
1336—07/21/08