ICS9UMS9610CKLFT Datasheet, PDF (11/20 Pages) Integrated Device Technology – PC MAIN CLOCK

ICS9UMS9610
PC MAIN CLOCK
Advance Information
Byte
Bit(s)
7
6
5
4
3
2
1
0
2 Output Enable Register
Pin #
Name
Description
Type
CPU0 Enable
This bit controls whether the CPU[0] output _RW
buffer is enabled or not.
CPU1 Enable
This bit controls whether the CPU[1] output _RW
buffer is enabled or not.
CPU2 Enable
This bit controls whether the CPU[2] output
buffer is enabled or not.
RW
SRC0 Enable
This bit controls whether the SRC[0] output _RW
buffer is enabled or not.
SRC1 Enable
This bit controls whether the SRC[1] output _RW
buffer is enabled or not.
SRC2 Enable
This bit controls whether the SRC[2] output _RW
buffer is enabled or not.
DOT Enable
This bit controls whether the DOT output
RW
buffer is enabled or not.
LCD100 Enable ^{This bit controls whether the LCD output buffer} RW
is enabled or not.
0
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
1
1 = Enabled
Default
1
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
Byte
Bit(s)
7
6
5
4
3
2
1
0
3 Output Control Register
Pin #
Name
Description
Reserved
Reserved
REF Enable
This bit controls whether the REF output
buffer is enabled or not.
REF Slew
These bits control the edge rate of the REF
clock.
CPU0 Stop
Enable
CPU1 Stop
Enable
This bit controls whether the CPU[0] output
buffer is free-running or stoppable. If it is set
to stoppable the CPU[0] output buffer will be
disabled with the assertion of CPU_STP#.
This bit controls whether the CPU[1] output
buffer is free-running or stoppable. If it is set
to stoppable the CPU[1] output buffer will be
disabled with the assertion of CPU_STP#.
Type
RW
RW
RW
RW
0
1
0 = Disabled 1 = Enabled
00 = Slow Edge Rate
01 = Medium Edge Rate
10 = Fast Edge Rate
11 = Reserved
Free Running Stoppable
Free Running Stoppable
CPU2 Stop
Enable
This bit controls whether the CPU[2] output
buffer is free-running or stoppable. If it is set
to stoppable the CPU[2] output buffer will be ^{RW Free Running}
disabled with the assertion of CPU_STP#.
Stoppable
Default
0
0
1
10
0
0
0
IDT^TM/ICST^M PC MAIN CLOCK
11
1336—07/21/08