ICS9UMS9610CKLFT Datasheet, PDF (10/20 Pages) Integrated Device Technology – PC MAIN CLOCK

ICS9UMS9610
PC MAIN CLOCK
Advance Information
Byte
Bit(s)
7
6
5
4
3
2
1
0
0 PLL & Divider Enable Register
Pin #
Name
Description
Type
-
PLL1 Enable
This bit controls whether the PLL driving the _RW
CPU and SRC clocks is enabled or not.
-
PLL2 Enable ^{This bit controls whether the PLL driving the} RW
DOT and clock is enabled or not.
-
PLL3 Enable
This bit controls whether the PLL driving the
LCD clock is enabled or not.
RW
-
Reserved
This bit controls whether the CPU output
-
CPU Divider
divider is enabled or not.
RW
Enable
NOTE: This bit should be automatically set to
‘0’ if bit 7 is set to ‘0’.
This bit controls whether the SRC output
-
SRC Output
divider is enabled or not.
RW
Divider Enable NOTE: This bit should be automatically set to
‘0’ if bit 7 is set to ‘0’.
This bit controls whether the LCD output
-
LCD Output
divider is enabled or not.
RW
Divider Enable NOTE: This bit should be automatically set to
‘0’ if bit 5 is set to ‘0’.
This bit controls whether the DOT output
-
DOT Output
divider is enabled or not.
RW
Divider Enable NOTE: This bit should be automatically set to
‘0’ if bit 6 is set to ‘0’.
0
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
1
1 = Enabled
Default
1
1 = Enabled
1
1 = Enabled
1
0
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
Byte
Bit(s)
7
6
5
4
3
2
1
0
1 PLL SS Enable/Control Register
Pin #
Name
Description
Type
0
1
This bit controls whether PLL1 has spread
PLL1 SS Enable ^{enabled or not. Spread spectrum for PLL1 is} RW 0 = Disabled
set at -0.5% down-spread. Note that PLL1
1 = Enabled
drives the CPU and SRC clocks.
This bit controls whether PLL3 has spread
PLL3 SS Enable ^{enabled or not. Note that PLL3 drives the SSC} RW 0 = Disabled
clock, and that the spread spectrum amount is
1 = Enabled
set in bits 3-5.
PLL3 FS Select
These 3 bits select the frequency of PLL3 and
the SSC clock when Byte 1 Bit 6 (PLL3
RW
See Table 2: LCD Spread Select
Table
Spread Spectrum Enable) is set.
Reserved
Reserved
Reserved
Default
1
1
0
0
0
0
0
0
IDT^TM/ICST^M PC MAIN CLOCK
10
1336—07/21/08