ICS9FG1904B-1 Datasheet, PDF (3/22 Pages) Integrated Circuit Systems – Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD

Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
Pin Description (Continued)
PIN #
PIN NAME
37 OE9#
38 DIF_9
39 DIF_9#
40 OE10#
41 DIF_10
42 DIF_10#
43 OE11#
44 DIF_11
45 DIF_11#
46 GND
47 VDD
48 OE12#
49 DIF_12
50 DIF_12#
51 OE13#
52 DIF_13
53 DIF_13#
54 OE14#
55 DIF_14
56 DIF_14#
57 CKPWRGD/PD#
58 DIF_15
59 DIF_15#
60 OE_15_16#
61 DIF_ 16
62 DIF_16#
63 VDD
64 GND
65 DIF_17
66 DIF_17#
67 DIF_18
68 DIF_18#
69 OE_17_18#
70 CLK_IN
71 CLK_IN#
72 SMB_A2_PLLBYP#
PIN TYPE
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
IN
IN
IN
DESCRIPTION
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 10.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 11.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Ground pin.
Power supply, nominal 3.3V
Active low input for enabling DIF pair 12.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 13.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 14.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
A rising edge samples latched inputs and release Power Down Mode, a low
puts the part into power down mode and tristates all outputs.
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 15 and 16.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 17, 18.
1 = tri-state outputs, 0 = enable outputs
Input for reference clock.
"Complementary" reference clock input.
SMBus address bit 2. When Low, the part operates as a fanout buffer with the
PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with
the PLL operating.
0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)
1255B—08/03/07
3