ICS9FG1904B-1 Datasheet, PDF (18/22 Pages) Integrated Circuit Systems – Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD

Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
SMBus Table: Gear PLL Frequency Control Register
Byte 12 Pin #
Name
Control Function
Bit 7
-
Gear PLL N Div7
Bit 6
-
Gear PLL N Div6
Bit 5
-
Gear PLL N Div5
Bit 4
-
Bit 3
-
Gear PLL N Div4
Gear PLL N Div3
N Divider
Bit 2
-
Gear PLL N Div2
Bit 1
-
Gear PLL N Div1
Bit 0
-
Gear PLL N Div0
Type
0
1
PWD
RW
X
RW
X
RW
X
RW See M/N Programming Section X
RW
of the Data Sheet
X
RW
X
RW
X
RW
X
SMBusTable: Reserved Register
Byte 13 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Gear PLL Out Div 3
Bit 2
Gear PLL Out Div 2
Bit 1
Gear PLL Out Div 1
Bit 0
Gear PLL Out Div 0
Control Function Type
0
1
PWD
RESERVED
0
RESERVED
0
RESERVED
0
RESERVED
0
Gear PLL Output Divider _RW
x
Gear PLL Output Divider _RW See Output Divider Ratios _x
Gear PLL Output Divider _RW
Table
x
Gear PLL Output Divider _RW
x
SMBusTable: Reserved Register
Byte 14 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function Type
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
1
PWD
0
0
0
0
0
0
0
0
SMBusTable: Reserved Register
Byte 15 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function Type
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
1
PWD
0
0
0
0
0
0
0
0
1255B—08/03/07
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