ICS9FG1904B-1 Datasheet, PDF (1/22 Pages) Integrated Circuit Systems – Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD

Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD
Recommended Application:
DB1900GS/GSO with 15:4 output grouping
Features:
• Power up default is all outputs in 1:1 mode
• DIF_(14:0) can be “gear-shifted” from the input CPU
Host Clock
• DIF_(18:15) can be “gear-shifted” from the input CPU
Host Clock
• Spread spectrum compatible
• Supports output clock frequencies up to 400 MHz
• 8 Selectable SMBus addresses
• SMBus address determines PLL or Bypass mode
Key Specifications:
• DIF output cycle-to-cycle jitter < 50ps
• DIF output-to-output skew < 100ps within a group
Functionality at Power Up (PLL Mode)
FS_A_410¹
1
0
CLK_IN (CPU FSB)
MHz
100 <= CLK_IN < 200
200<= CLK_IN <= 400
DIF_(18:0)
MHz
CLK_IN
CLK_IN
1. FS_A_410 is a low-threshold input. Please see the V_{IL_FS} and V_{IH_FS}
specifications in the Input/Supply/Common Output Parameters Table for
correct values.
Power Down Functionality
INPUTS
CKPWRGD/ CLK_IN/
PD#
CLK_IN#
1
Running
0
X
OUTPUTS
DIF/DIF#
Running
Hi-Z
PLL State
ON
OFF
Pin Configuration
IREF
GNDA
VDDA
HIGH_BW#
FS_A_410
DIF_0
DIF_0#
DIF_1
DIF_1#
GND
VDD
DIF_2
DIF_2#
DIF_3
DIF_3#
DIF_4
DIF_4#
OE_01234#
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
1
2
3
4
5
6
7
8
9
10
ICS9FG1904-1
11
12
13
14
15
16
17
18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
54 OE14#
53 DIF_13#
52 DIF_13
51 OE13#
50 DIF_12#
49 DIF_12
48 OE12#
47 VDD
46 GND
45 DIF_11#
44 DIF_11
43 OE11#
42 DIF_10#
41 DIF_10
40 OE10#
39 DIF_9#
38 DIF_9
37 OE9#
1255B—08/03/07
72-pin MLF
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