ICS9FG1904B-1 Datasheet, PDF (12/22 Pages) Integrated Circuit Systems – Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD

Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
Using M/N Programming to Obtain Other Gear Ratios
M/N programming can be used to obtain input output frequency combinations that are not preconfigured in the
9FG1904B-1. Refer to Figure 2 PLL Block Diagram.
The internal architecture of the 9FG1904B-1 is standard pseudo-ZDB architecture with internal feedback. This means
that the REF divider, the Output divider and the Feedback divider all play a role in determining the output frequency.
The output frequency is given by the equation:
Output Frequency = (Input Frequency x N x Output Div)/M
Input
Clock
REF (M)
DIV
FBK (N)
DIV
vco
OUTPUT
DIV
BUFFERS
Output
Clocks
Figure 2 PLL Block Diagram
The DBxxxxGSO input/output combinations that are not in the 9FG1904B-1 gear table are shown in Table 1 DBxxxxGSO
Gears Not Present in the 9FG1904B-1. This table also gives the values needed to program the gearing PLL to provide
the desired input/output combination.
1:1 PLL Bytes
Gear PLL Bytes
Byte
17
Byte
11
Byte
18
Byte
12
Byte
19
Byte
13
Line
1 0 133.33 400.00 4 12 2 3.000 2
A
0
2 1 400.00 200.00 12 6 4 0.500 A
4
4
3 1 400.00 266.67 12 8 3 0.667 A
6
1
Table 1 DBxxxxGSO Gears Not Present in the 9FG1904B-1
Note before the M/N programming can be accomplished, Byte 10, bit 7 (the M/N_Enable bit) must be set to a ‘1’. The
values provided in the table above have been verified to meet the specified performance of the 9FG1901B-1.
Performance is not guaranteed for any other values that have not been pre-approved by IDT. Contact your local IDT
representative for other values not mentioned here.
Setting the 1:1 PLL Operating Point
After configuring the Gearing outputs, it is also necessary to set the 1:1 PLL operating point by writing the input
frequency value to Byte 9 bits (2:0). The input frequency is usually the CPU HCLK frequency.
1255B—08/03/07
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