ICS9FG1904B-1 Datasheet, PDF (19/22 Pages) Integrated Circuit Systems – Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD

Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
SMBusTable: Reserved Register
Byte 16 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function Type
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
1
PWD
0
0
0
0
0
0
0
0
SMBus Table: 1:1 PLL Frequency Control Register
Byte 17 Pin #
Name
Control Function
Bit 7
RESERVED
Bit 6
RESERVED
Bit 5
-
1:1 PLL M Div5
Bit 4
-
1:1 PLL M Div4
Bit 3
-
1:1 PLL M Div3 M Divider Programming
Bit 2
-
1:1 PLL M Div2
bits
Bit 1
-
1:1 PLL M Div1
Bit 0
-
1:1 PLL M Div0
Type
0
1
PWD
X
X
RW
X
RW
X
RW See M/N Programming Section X
RW
of the Data Sheet
X
RW
X
RW
X
SMBus Table: 1:1 PLL Frequency Control Register
Byte 18 Pin #
Name
Control Function
Bit 7
-
1:1 PLL N Div7
Bit 6
-
1:1 PLL N Div6
Bit 5
-
1:1 PLL N Div5
Bit 4
-
1:1 PLL N Div4 N Divider Programming
Bit 3
-
1:1 PLL N Div3
b(7:0)
Bit 2
-
1:1 PLL N Div2
Bit 1
-
1:1 PLL N Div1
Bit 0
-
1:1 PLL N Div0
Type
0
1
PWD
RW
X
RW
X
RW
X
RW See M/N Programming Section X
RW
of the Data Sheet
X
RW
X
RW
X
RW
X
SMBusTable: Reserved Register
Byte 19 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
1:1 PLL Out Div 3
Bit 2
1:1 PLL Out Div 2
Bit 1
1:1 PLL Out Div 1
Bit 0
1:1 PLL Out Div 0
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
1:1 PLL Output Divider
1:1 PLL Output Divider
1:1 PLL Output Divider
1:1 PLL Output Divider
Type
0
1
PWD
0
0
0
0
RW
x
RW ^{See Output Divider Ratios} x
RW
Table
x
RW
x
1255B—08/03/07
19