ICS843207-350 Datasheet, PDF (3/16 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER

ICS843207-350
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
TABLE 2. PIN DESCRIPTIONS
Number
1, 7, 12,
25, 30, 34
Name
V
CCO
Type
Power
Descriptionn
Output supply pins.
2, 3
Q0, nQ0
Ouput
Differential output pair. LVPECL interface levels.
4, 5
Q1, nQ1
Ouput
Differential output pair. LVPECL interface levels.
6, 16, 31
8, 9
V_EE
Q2, nQ2
Power
Ouput
Negative supply pins.
Differential output pair. LVPECL interface levels.
10, 11
Q3, nQ3
Ouput
Differential output pair. LVPECL interface levels.
13
MODE
Input
Pulldown
MODE pin. LOW = default mode. HIGH = frequency margining mode.
See Table 4B. LVCMOS/LVTTL interface levels.
14
Margin
Input
Pulldown
Sets the frequency to ±5% in frequency margining mode.
See Table 1B. LVCMOS/LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are
15
MR
Input
Pulldown
reset causing the true outputs Qx to go LOW and inverted outputs
nQx to go HIGH. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS/LVTTL interface levels.
17
REF_CLK
Input Pulldown Reference input clock. LVCMOS/LVTTL interface levels.
18
nXTAL_SEL
Input
Pulldown
Crystal select pin. Selects between the crystal and the reference
clock inputs. LVCMOS/LVTTL interface levels.
19,
20
XTAL_OUT,
XTAL_IN
Input
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
21, 35
22
23, 24,
37, 38,
39, 40,
41, 42,
43, 44,
45, 46,
47, 48
V_CC
nPLL_SEL
SEL0, SEL1,
SEL2, SEL3,
SEL4, SEL5,
SEL6, SEL7,
SEL8, SEL9,
SEL10, SEL11,
SEL12, SEL13
Power
Input
Input
Core supply pins.
PLL select pin. When HIGH, PLL is bypassed and input is fed directly
Pulldown to the output dividers. When LOW, PLL is enabled.
LVCMOS/LVTTL interface levels.
Pullup
Output divider select pins. See Table 1A.
LVCMOS/LVTTL interface levels.
26, 27
Q4, nQ4
Ouput
Differential output pair. LVPECL interface levels.
28, 29
Q5, nQ5
Ouput
Differential output pair. LVPECL interface levels.
32, 33
Q6, nQ6
Ouput
Differential output pair. LVPECL interface levels.
36
V_CCA
Power
Analog supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol Parameter
C_IN
R_PULLDOWN
R_PULLUP
Input Capacitance
Input Pulldown Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 4A. nXTAL_SEL CONTROL INPUT FUNCTION TABLE
Input
nXTAL_SEL
Selected Source
0
XTAL_IN, XTAL_OUT
1
REF_CLK
TABLE 4B. MODE CONTROL INPUT FUNCTION TABLE
Input
Condition
MODE
Q0:Q6, nQ0:nQ6
0
Default Mode
1
Frequency Margining Mode
IDT^™ / ICS^™ LVPECL FREQUENCY MARGINING SYNTHESIZER
3
ICS843207CY-350 REV. A DECEMBER 3, 2007