ICS843207-350 Datasheet, PDF (1/16 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER

FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
350MHZ FREQUENCY MARGINING SYNTHESIZER
ICS843207-350
GENERAL DESCRIPTION
The ICS843207-350 is a low phase-noise
ICS
frequency margining synthesizer that targets
HiPerClockS™ clocking for high perfor mance interfaces such
as SPI4.2 and is a member of the HiPerClockS™
family of high performance clock solutions from
IDT. In the default mode, each output can be configured
individually to generate an 87.5MHz, 175MHZ or 350MHz
LVPECL output clock signal from a 14MHz crystal input.
There is also a frequency margining mode available where
the device can be configured, using control pins, to vary
the output frequency up or down from nominal by 5%. The
ICS843207-350 is provided in a 48-pin LQFP package.
PIN ASSIGNMENT
FEATURES
• Seven independently configurable LVPECL outputs at
87.5MHz, 175MHz or 350MHz
• Individual high impedance control of each output
• Selectable crystal oscillator interface designed for 14MHz,
18pF parallel resonant crystal or LVCMOS single-ended input
• Output frequency can be varied ± 5% from nominal
• VCO range: 620MHz - 750MHz
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
48 47 46 45 44 43 42 41 40 39 38 37
VCCO 1
36 VCCA
Q0 2
35 VCC
nQ0 3
Q1 4
34 VCCO
ICS843207-350 33 nQ6
nQ1 5
48-Pin LQFP
32 Q6
VEE 6
VCCO 7
Q2 8
nQ2 9
7mm x 7mm x 1.4mm 31 ^VEE
package body
30 VCCO
Y Package
Top View
29 nQ5
28 Q5
Q3 10
27 nQ4
nQ3 11
26 Q4
VCCO 12
25 VCCO
13 14 15 16 17 18 19 20 21 22 23 24
nPLL_SEL ^Pulldown
14MHz
XTAL_IN
OSC ₀
XTAL_OUT
REF_CLK ^Pulldown
1
nXTAL_SEL ^Pulldown
MODE ^Pulldown
MARGIN ^Pulldown
MR ^Pulldown
BLOCK DIAGRAM
1
0
Predivider
Phase
VCO
÷2
1
Detector
620 - 750MHz
0
0 ÷50
÷95
1
÷105
To O/P Dividers
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pullup
Q0
nQ0
2 _SEL[1:0]
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pullup
Q1
nQ1
2 _SEL[3:2]
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pullup
Q2
nQ2
2 _SEL[5:4]
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pullup
Q3
nQ3
2 _SEL[7:6]
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pullup
Q4
nQ4
2 _SEL[9:8]
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pullup
Q5
nQ5
2 _SEL[11:10]
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pullup
Q6
nQ6
2 _SEL[13:12]
IDT^™ / ICS^™ LVPECL FREQUENCY MARGINING SYNTHESIZER
1
ICS843207CY-350 REV. A DECEMBER 3, 2007