932SQ426_16 Datasheet, PDF (3/25 Pages) Integrated Device Technology – DERIVATIVE SUPPORTING SRNS PCIE CLOCKING

932SQ426
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING
Pin Descriptions (TSSOP)
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PIN NAME
TYPE
DESCRIPTION
SMBCLK
IN Clock pin of SMBUS circuitry, 5V tolerant
GND14
PWR Ground pin for 14MHz output and logic.
AVDD14
PWR Analog power pin for 14MHz PLL
VDD14
PWR Power pin for 14MHz output and logic
vREF14_3x/TEST_SEL I/O ^{14.318 MHz reference clock. 3X drive strength as default / TEST_SEL latched input to enable test mode.}
Refer to Test Clarification Table. This pin has a weak (~120Kohm) internal pull down.
GND14
PWR Ground pin for 14MHz output and logic.
GNDXTAL
PWR Ground pin for Crystal Oscillator.
X1_25
IN Crystal input, Nominally 25.00MHz.
X2_25
OUT Crystal output, Nominally 25.00MHz.
VDDXTAL
PWR 3.3V power for the crystal oscillator.
GNDPCI
PWR Ground pin for PCI outputs and logic.
VDDPCI
PWR 3.3V power for the PCI outputs and logic
PCI4_2x
OUT 3.3V PCI clock output
PCI3_2x
OUT 3.3V PCI clock output
PCI2_2x
OUT 3.3V PCI clock output
PCI1_2x
OUT 3.3V PCI clock output
PCI0_2x
OUT 3.3V PCI clock output
GNDPCI
PWR Ground pin for PCI outputs and logic.
VDDPCI
PWR 3.3V power for the PCI outputs and logic
VDD48
PWR 3.3V power for the 48MHz output and logic
48M_2x
OUT 3.3V 48MHz output
GND48
PWR Ground pin for 48MHz output and logic.
GND96
PWR Ground pin for DOT96 output and logic.
True clock of differential 96MHz output. These are current mode outputs and external series resistors
DOT96T
OUT and shunt resistors are required for termination. See Test Loads and Recommended Terminations for
specific values.
Complementary clock of differential 96MHz output. These are current mode outputs and external series
DOT96C
OUT resistors and shunt resistors are required for termination. See Test Loads and Recommended
Terminations for specific values.
AVDD96
PWR 3.3V power for the 48/96MHz PLL and the 96MHz output and logic
TEST_MODE
IN ^{TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode.}
Refer to Test Clarification Table.
CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power Up. PD is
CKPWRGD#/PD
IN an asynchronous active high input pin used to put the device into a low power state. The internal clocks
and PLLs are stopped.
VDDSRC
PWR 3.3V power for the SRC outputs and logic
True clock of differential SRC output. These are current mode outputs and external series resistors and
SRC0T
OUT shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific
values.
Complementary clock of differential SRC output. These are current mode outputs and external series
SRC0C
OUT resistors and shunt resistors are required for termination. See Test Loads and Recommended
Terminations for specific values.
GNDSRC
PWR Ground pin for SRC outputs and logic.
Complementary clock of differential SRC output. These are current mode outputs and external series
SRC1C
OUT resistors and shunt resistors are required for termination. See Test Loads and Recommended
Terminations for specific values.
True clock of differential SRC output. These are current mode outputs and external series resistors and
SRC1T
OUT shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific
values.
Complementary clock of differential SRC output. These are current mode outputs and external series
SRC2C
OUT resistors and shunt resistors are required for termination. See Test Loads and Recommended
Terminations for specific values.
True clock of differential SRC output. These are current mode outputs and external series resistors and
SRC2T
OUT shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific
values.
VDDSRC
PWR 3.3V power for the SRC outputs and logic
AVDD_SRC
PWR 3.3V power for the SRC PLL analog circuits
GNDSRC
PWR Ground pin for SRC outputs and logic.
This pin establishes the reference current for the differential current-mode output pairs. This pin requires a
IREF
OUT fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the
standard value.
IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING
3
932SQ426
REV C 022916