932SQ426_16 Datasheet, PDF (12/25 Pages) Integrated Device Technology – DERIVATIVE SUPPORTING SRNS PCIE CLOCKING

932SQ426
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING
AC Electrical Characteristics - Differential Current Mode Outputs
TA = T_COM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Duty Cycle
t_DC
Measured differentially, PLL Mode
45
52
55
%
1
Skew, Output to
Output
t_sk3SRC
Across all SRC, NS-SAS outputs, V_T =
50%
12
50
ps
1
Skew, Output to
Output
t_sk3CPU
Across all CPU outputs, V_T = 50%
35
50
ps
1
Jitter, Cycle to cycle t_jcyc-cyc
CPU, SRC, NS_SAS outputs @100M
DOT96 output
34
50
ps
1,3
75
250
ps
1,3
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{IREF = VDD/(3xRR). For RR =412Ω (1%), IREF = 2.67mA. IOH = 6 x IREF and VOH = 0.7V @ ZO= 85Ω differential impedance.}
3 _{Measured from differential waveform}
Electrical Characteristics - Phase Jitter Parameters
T_A = 0 - 70°C; Supply Voltage V_DD/V_DDA = 3.3 V +/-5%,
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS Notes
t_jphPCIeG1
PCIe Gen 1
16
86 ps (p-p) 1,2,3,6
Phase Jitter
t_jphPCIeG2
t_jphPCIeG3
t_{jphQPI_SMI}
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s
12UI)
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
0.37
3
ps
1,2,6
(rms)
1.45
3.1
ps
(rms)
1,2,6
0.35
1
ps _1,2,4,6
(rms)
ps
0.29
0.5
(rms) ^1,5,6
0.15
0.3
ps
1,5,6
(rms)
0.13
0.2
ps
1,5,6
(rms)
SAS12G
t_{jphSAS12G (Filtered REFCLK Jitter 20KHz to 20MHz.)}
ps
0.30
0.4
(rms) ^1,7,8
t_jphSAS12G
SAS 12G
0.54
1.3
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{See http://www.pcisig.com for complete specs}
3 _{Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.}
4 _{Subject to final radification by PCI SIG.}
ps
(rms)
5 _{Calculated from Intel-supplied Clock Jitter Tool v 1.6.4}
6 _{Applies to CPU, SRC and NS_SAS outputs}
7 _{Intel calculation from raw phase noise data}
8 _{Applies to NS_SAS and NS_SRC outputs only.}
1,5,8
IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING
12
932SQ426
REV C 022916