932SQ426_16 Datasheet, PDF (14/25 Pages) Integrated Device Technology – DERIVATIVE SUPPORTING SRNS PCIE CLOCKING

932SQ426
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING
Electrical Characteristics - REF
T_A = 0 - 70°C; Supply Voltage V_DD/V_DDA = 3.3 V +/-5%,
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
R_DSP
V_O = V_DD*(0.5)
Output High Voltage
V_OH
I_OH = -1 mA
Output Low Voltage
V_OL
I_OL = 1 mA
Clock High Time
T_HIGH
1.5V
Clock Low Time
T_LOW
1.5V
Edge Rate
t_slewr/f
Rising/Falling edge rate
Duty Cycle
d_t1
V_T = 1.5 V
Jitter, Cycle to cycle tjcyc-cyc
V_T = 1.5 V
See "Single-ended Test Loads Page" for termination circuits
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Measured between 0.8V and 2.0V}
MIN
TYP
MAX UNITS Notes
12
55
Ω
1
2.4
V
0.55
V
27.5
ns
1
27.5
ns
1
1
1.5
4
V/ns 1,2
45
50.5
55
%
1
89
1000
ps
1
Clock AC Tolerances
PPM tolerance
Cycle to Cycle Jitter
CPU
100
50
SRC,
NS_SAS,
NS_SRC
PCI
100
100
50
500
DOT96
100
250
48MHz
100
350
REF
100
1000
ppm
ps
Clock Periods – Outputs without Spread Spectrum
SSC ON
Center
Freq.
MHz
CPU
SRC,
NS_SAS,
NS_SRC
PCI
DOT96
48MHz
REF
100.00000
100.00000
33.33333
96.00000
48.00000
14.31818
1 Clock
-c2c jitter
AbsPer
Min
9.94900
9.94900
29.49700
10.16563
20.48125
69.78429
Measurement Window
1us
0.1s
0.1s
0.1s
-SSC
- ppm
Short-Term Long-Term
Average Average
Min
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
9.99900 10.00000 10.00100
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.05100 ns 1,2
9.99900 10.00000
29.99700
10.41563
20.83125
69.83429
30.00000
10.41667
20.83333
69.84128
10.00100
30.00300
10.41771
20.83542
69.84826
10.05100 ns
1,2
30.50300 ns 1,2
10.66771 ns 1,2
21.18542 ns 1,2
69.89826 ns 1,2
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{All Long Term Accuracy specifications are guaranteed with the assumption that the REF output is tuned to exactly 14.31818MHz.}
IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING
14
932SQ426
REV C 022916