932SQ426_16 Datasheet, PDF (20/25 Pages) Integrated Device Technology – DERIVATIVE SUPPORTING SRNS PCIE CLOCKING

932SQ426
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING
Test Clarification Table
Comments
Power-up w/ TEST_SEL = 1 (>2.0V) to enter test
mode. Cycle power to disable test mode.
If TEST_SEL HW pin is 0 during power-up,
test mode can be selected through B6b6.
If test mode is selected by B6b6, then B6b7
is used to select HI-Z or REF/N.
TEST_Mode pin is not used.
Cycle power to disable test mode.
HW
SW
TEST_SEL 932SQ426A ENTRY BIT
HW PIN
KLF
B6b6
0
X
0
HI-Z
B6b7
X
1
0
X
0
1
0
X
1
1
1
X
0
1
1
X
1
0
X
1
0
0
X
1
1
B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B6b7: 1= REF/N, Default = 0 (HI-Z)
OUTPUT
NORMAL
HI-Z
REF/N
REF/N
REF/N
HI-Z
REF/N
Marking Diagrams
ICS _LOT
YYWW
932SQ426AGLF
ICS
932SQ426AKL
LOT
COO YYWW
Notes:
1. “LOT” denotes lot number.
2. “YYWW” is the date code.
3. “COO” denotes country of origin.
4. “L” or “LF” denotes RoHS compliant package.
IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING
20
932SQ426
REV C 022916