ICS9LPRS480 Datasheet, PDF (22/25 Pages) Integrated Device Technology – Programmable System Clock Chip for ATI RS780 - K8TM based Systems

Integrated
Circuit
Systems, Inc.
ICS9LPRS480
Byte
22
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: CLKREQ# Configuration Register
Name
Control Function
CPU/HTT/SRC/ATIG M/N En
SB_SRC M/N En
CPU/HTT/SRC/ATIG PLL
M/N Prog. Enable
SB_SRC M/N Prog. Enable
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
M/N Prog. Disabled
M/N Prog. Disabled
-
-
-
-
-
-
1
M/N Prog. Enabled
M/N Prog. Enabled
-
-
-
-
-
-
Default
0
0
0
0
0
X
X
X
Byte
23
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: CLKREQ# Configuration Register
Name
Control Function Type
Reserved
Reserved
RW
Reserved
Reserved
RW
Reserved
Reserved
RW
CLKREQ4#_Enable
CLKREQ4# controls SRC4 RW
CLKREQ3#_Enable
CLKREQ3# controls SRC3 RW
CLKREQ2#_Enable
CLKREQ2# controls SRC2 RW
CLKREQ1#_Enable
CLKREQ1# controls SRC1 RW
CLKREQ0#_Enable
CLKREQ0# controls SRC0 RW
0
-
-
-
Not Controlled
Not Controlled
Not Controlled
Not Controlled
Not Controlled
1
-
-
-
Controlled
Controlled
Controlled
Controlled
Controlled
Default
0
0
0
0
0
0
0
0
Byte
24
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: Test Mode Configuration Register
Name
Test_Md_Sel
Control Function
Selects Test Mode
Type
RW
DIAG Enable#
DIAG enable
CPU and LCD PLL
RW
CPU PLL_LOCK signal
27MHz PLL_LOCK signal
Fixed PLL_LOCK signal
SRC PLL_LOCK signal
CPU PLL Lock Detect
R
27MHz PLL Lock Detect R
Fixed PLL Lock Detect
R
Fixed PLL Lock Detect
R
0
Normal mode
Reset forces
B24[6:4,2,0]
to 0
unlocked
unlocked
unlocked
unlocked
1
Default
All ouputs are REF/N
0
DIAG mode Enabled
0
Locked
HW
Locked
HW
Locked
HW
Locked
HW
Frequency Check
Primary PLL or external
crystal Frequency Accuracy
R
Not Accurate
Accurate
HW
PWRGD Status
Power on Reset Status
Invalid voltage levels on Valid voltage levels
any of the VDDs.
exist on all the VDD.
R
CKPWRGD is not CKPWRGD is asserted HW
asserted or external and external XTAL is
XTAL not detected.
detected.
Byte
25
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table:Slew Rate Select Register
Name
Control Function
Reserved
Reserved
Reserved
Reserved
REF2_Slew Rate
Slew Rate Control
REF1_Slew Rate
Slew Rate Control
REF0_Slew Rate
Slew Rate Control
Type
0
1
RW
-
-
RW
-
-
RW ^{These bits program the slew rate of the single}
ended outputs. The maximum slew rate is
1.9V/ns and the minimum slew rate is 1.1V/ns.
RW
The slew rate selection is as follows:
11 = 1.9V/ns
10 = 1.6V/ns
01 = 1.1V/ns
RW
00 = tristated
Default
0
0
1
1
1
1
1
1
1391D—02/02/09
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