ICS9LPRS480 Datasheet, PDF (20/25 Pages) Integrated Device Technology – Programmable System Clock Chip for ATI RS780 - K8TM based Systems

Integrated
Circuit
Systems, Inc.
ICS9LPRS480
Byte
12
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: CPU PLL Frequency Control Register
Name
Control Function Type
0
1
Default
N Div10
RW
X
N Div9
RW
X
N Div8
N Div7
N Div6
N Div5
RW _{The decimal representation of M and N Divider in}
X
N Divider Programming ^RW Byte 11 and 12 will configure the VCO frequency.
X
b(10:3)
RW Default at power up = Byte 3 Rom table. VCO
X
RW ^{Frequency = 14.318 x Ndiv(10:0)/Mdiv(5:0) .}
X
N Div4
RW
X
N Div3
RW
X
Byte
13
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: CPU PLL Spread Spectrum Control Register
Name
Control Function Type
0
1
SSP7
RW
SSP6
RW
SSP5
SSP4
SSP3
SSP2
Spread Spectrum
Programming b(7:0)
RW
RW
Bytes 13 and 14 set the CPU/HTT/SRC/ATIG
spread pecentage.Please contact ICS for the
RW
appropriate values.
RW
SSP1
RW
SSP0
RW
Default
X
X
X
X
X
X
X
X
Byte
14
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: CPU PLL Spread Spectrum Control Register
Name
Control Function Type
0
1
Reserved
SSP14
RW
SSP13
RW
SSP12
SSP11
SSP10
Spread Spectrum
Programming b(14:8)
RW Bytes 13 and 14 set the CPU/HTT/SRC/ATIG
RW spread pecentage.Please contact ICS for the
RW
appropriate values.
SSP9
RW
SSP8
RW
Default
X
X
X
X
X
X
X
X
Byte
15
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBUS Table: CPU Output Divider Register
Name
Control Function Type
CPU NDiv0
LSB N Divider Programming RW
Reserved
Reserved
Reserved
CPUDiv3
RW
CPUDiv2
CPUDiv1
CPU Divider Ratio
RW
Programming Bits
RW
CPUDiv0
RW
0
1
CPU M/N programming.
0000:/2 ; 0100:/4
0001:/3 ; 0101:/6
0010:/5 ; 0110:/10
0011:/15 ; 0111:/18
1000:/8 ; 1100:/16
1001:/12 ; 1101:/24
1010:/20 ; 1110:/40
1011:/36 ; 1111:/72
Default
X
X
X
X
X
X
X
X
Byte
16
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBUS Table: SB_SRC Frequency Control Register
Name
Control Function Type
N Div2
N Divider Prog bit 2
RW
N Div1
N Divider Prog bit 1
RW
M Div5
RW
M Div4
RW
M Div3
M Div2
M Divider Programming RW
bit (5:0)
RW
M Div1
RW
M Div0
RW
0
1
The decimal representation of M and N Divider in
Byte 16 and 17 configure the SB_SRC VCO
frequency. See M/N Caculation Tables for VCO
frequency formulas.
Default
X
X
X
X
X
X
X
X
1391D—02/02/09
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