ICS9LPRS480 Datasheet, PDF (19/25 Pages) Integrated Device Technology – Programmable System Clock Chip for ATI RS780 - K8TM based Systems

Integrated
Circuit
Systems, Inc.
ICS9LPRS480
Byte
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: Byte Count Register
Name
Control Function Type
Reserved
Reserved
BC5
Byte Count bit 5 (MSB) RW
BC4
Byte Count bit 4
RW
BC3
Byte Count bit 3
RW
BC2
Byte Count bit 2
RW
BC1
Byte Count bit 1
RW
BC0
Byte Count bit 0 (LSB) RW
0
1
Determines the number of bytes that are read
back from the device. Default is 0F hex.
Default
0
0
0
0
1
1
1
1
Byte
9
Bit 7
SMBus Table: WatchDog Timer Control Register
Name
Control Function Type
0
HWD_EN
Watchdog Hard Alarm
Enable
Disable and Reload
RW Hartd Alarm Timer, Clear
WD Hard status bit.
1
Enable Timer
Default
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SWD_EN
WD Hard Status
WD Soft Status
WDTCtrl
HWD2
HWD1
HWD0
Watchdog Soft Alarm Enable RW
Disable
Enable
0
WD Hard Alarm Status
R
Normal
Alarm
X
WD Soft Alarm Status
R
Normal
Alarm
X
Watch Dog Alarm Time base
Control
RW
290ms Base
1160ms Base
0
WD Hard Alarm Timer Bit 2 RW These bits represent the number of Watch Dog
1
WD Hard Alarm Timer Bit 1 RW Time Base Units that pass before the Watch
1
WD Hard Alarm Timer Bit 0 RW
Alarm expires. Default is 7 X 290ms = 2s.
1
Byte
10
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: WD Timer Safe Frequency Control Register
Name
Control Function Type
0
1
SWD2
SWD1
SWD0
WD Soft Alarm Timer Bit 2 RW These bits represent the number of Watch Dog
WD Soft Alarm Timer Bit 1 RW Time Base Units that pass before the Watch
WD Soft Alarm Timer Bit 0 RW
Alarm expires. Default is 7 X 290ms = 2s.
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
Watch Dog Safe Freq
Programming bits
RW _{These bits configure the safe frequency that the}
RW device returns to if the Watchdog Timer expires.
RW The value show here corresponds to the power
RW
up default of the device. See the various
Frequency Select Tables for the exact
RW
frequencies.
Default
1
1
1
0
0
1
1
1
Byte
11
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: CPU PLL Frequency Control Register
Name
Control Function Type
0
1
Default
N Div2
N Divider Prog bit 2
RW
X
N Div1
N Divider Prog bit 1
RW
X
M Div5
M Div4
RW The decimal representation of M and N Divider in
X
RW Byte 11 and 12 will configure the VCO frequency. X
M Div3
M Div2
M Divider Programming bits ^RW
RW
Default at power up = Byte 3 Rom table. VCO
Frequency = 14.318 x Ndiv(10:0)/Mdiv(5:0) .
X
X
M Div1
RW
X
M Div0
RW
X
1391D—02/02/09
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