ICS8N3PG10MBKI-062 Datasheet, PDF (2/20 Pages) Integrated Device Technology – One differential LVPECL output pair

ICS8N3PG10MBKI-062 DATA SHEET
Pin Descriptions and Characteristics
Table 2. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
Name
OE
Reserved
V_EE
nCLK
CLK
Q
nQ
V_CC
FSEL0
FSEL1
Type
Pullup
Reserve
Power
Input
Input
Output
Output
Power
Pullup/
Pulldown
Pulldown
Input
Pullup
Input
Pullup
Description
Output enable. External pullup required for normal operation.
LVCMOS/LVTTL interface levels.
Reserved pin.
Negative supply pin.
Inverting differential clock input. V_CC/2 default when left floating
Non-inverting differential clock input.
Differential output pair. LVPECL interface levels.
Power supply pin.
Feedback control input. Sets the output divider value to one of four values.
LVCMOS/LVTTL interface levels. See Frequency Select Table on page 1.
Feedback control input. Sets the output divider value to one of four values.
LVCMOS/LVTTL interface levels. See Frequency Select Table on page 1.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 3. Pin Characteristics
Symbol
Parameter
C_IN
R_PULLUP
R_PULLDOWN
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
3.5
51
51
Maximum
Units
pF
k
k
Function Table
Table 4. P, M, N Divider Function Table
FSEL[1:0]
P
00
÷2
01
÷1
10
÷1
1 1 (default)
÷1
M
24
20
21.7727981
24.8831981
N
Input Frequency
(MHz)
Output Frequency
(MHz)
÷16
200
150
÷16
100
125
÷14
100
155.52
÷8
100
311.04
PROGRAMMABLE FEMTOCLOCK^® NG DIFFERENTIAL-TO-3.3V, 2.5V
2
LVPECL SYNTHESIZER
REV A 05/15/14