ICS8N3PG10MBKI-062 Datasheet, PDF (10/20 Pages) Integrated Device Technology – One differential LVPECL output pair

ICS8N3PG10MBKI-062 DATA SHEET
3.3V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both V_SWING and V_OH must meet the V_PP and
V_CMR input requirements. Figure 2A to Figure 2E show interface
examples for the CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 2A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
1.8V
Zo = 50Ω
Zo = 50Ω
LVHSTL
IDT
LVHSTL Driver
3.3V
CLK
R1
R2
50Ω
50Ω
nCLK
Differential
Input
Figure 2A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
R2
50Ω
50Ω
nCLK
Differential
Input
R2
50Ω
Figure 2D. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
LVPECL
3.3V
3.3V
CLK
nCLK
Differential
Input
3.3V
*R3
*R4
HCSL
3.3V
CLK
nCLK
Differential
Input
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
CLK
nCLK
Receiver
Figure 2C. CLK/nCLK Input Driven by a 3.3V LVDS Driver
PROGRAMMABLE FEMTOCLOCK^® NG DIFFERENTIAL-TO-3.3V, 2.5V
10
LVPECL SYNTHESIZER
REV A 05/15/14