ICS8N3PG10MBKI-062 Datasheet, PDF (13/20 Pages) Integrated Device Technology – One differential LVPECL output pair

ICS8N3PG10MBKI-062 DATA SHEET
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible signals. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figure 5A and Figure 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
3.3V
LVPECL
3.3V
R3
R4
125
125
3.3V
Z_o = 50
+
Z_o = 50
R1
84
_
R2
84
Input
Figure 5A. 3.3V LVPECL Output Termination
Figure 5B. 3.3V LVPECL Output Termination
REV A 05/15/14
13
PROGRAMMABLE FEMTOCLOCK^® NG DIFFERENTIAL-TO-3.3V, 2.5V
LVPECL SYNTHESIZER