ICS831724I Datasheet, PDF (15/24 Pages) Integrated Device Technology – LVCMOS interface levels for all control inputs

ICS831724I Data Sheet
DIFFERENTIAL CLOCK DATA MULTIPLEXER
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, HCSL, and other differential
signals. Both differential inputs must meet the V_PP and V_CMR input
requirements. Figures 2A to 2D show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 2A, the input termination
applies for IDT LVPECL drivers. If you are using an LVPECL driver
from another vendor, use their termination recommendation.
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
R2
50Ω
50Ω
nCLK
Differential
Input
R2
50Ω
Figure 2A. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
CLK
nCLK
Receiver
3.3V
LVPECL
3.3V
3.3V
CLK
nCLK
Differential
Input
Figure 2B. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
*R3
*R4
HCSL
CLK
nCLK
Differential
Input
Figure 2C. CLK/nCLK Input
Driven by a 3.3V LVDS Driver
Figure 2D. CLK/nCLK Input
Driven by a 3.3V HCSL Driver
ICS831724AKI REVISION A MAY 16, 2013
15
©2013 Integrated Device Technology, Inc