ICS9FG107 Datasheet, PDF (9/14 Pages) Integrated Circuit Systems – Programmable FTG for Differential CPU, PCI Express & SATA Clocks

Integrated
Circuit
Systems, Inc.
ICS9FG107
I²C Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Pin #
27
5
44
7
26
Name
Control
Function
FS3¹
FS2¹
FS1¹
FS0¹
Spread Enable¹
Type
RW
RW
RW
RW
RW
0
1
See Frequency
Selection Table, Page 1
Off
On
Bit 2
Enable Software Control of
-
Frequency, Spread Enable and
Spread Type
Hardware Software
RW
Select
Select
Bit 1
Bit 0
45
DIF_STOP# drive mode
DWNSPRD#¹
RW
Driven
RW
Down
Hi-Z
Center
PWD
Pin 27
Pin 5
Pin 44
Pin 7
Pin 26
0
0
Pin 45
Notes:
1. These bits reflect the latched state of the corresponding pins at power up, but may be written to
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.
I²C Table: Output Enable Register
Byte 1
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
8
12,13
17,18
20,21
30,29
33,32
39,38
42,41
PCICLK0
DIF_6
DIF_5
DIF_4
DIF_3
DIF_2
DIF_1
DIF_0
Control
Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Stop Low
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
I²C Table: Output Stop Mode Register
Byte 2
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
12,13
17,18
20,21
30,29
33,32
39,38
42,41
PCICLK1
DIF_6
DIF_5
DIF_4
DIF_3
DIF_2
DIF_1
DIF_0
Control
Function
Output Enable
Stop Mode
Stop Mode
Stop Mode
Stop Mode
Stop Mode
Stop Mode
Stop Mode
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Stop Low
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
1
Enable
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
PWD
1
0
0
0
0
0
0
0
0863C—11/22/04
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