ICS9FG107 Datasheet, PDF (10/14 Pages) Integrated Circuit Systems – Programmable FTG for Differential CPU, PCI Express & SATA Clocks

Integrated
Circuit
Systems, Inc.
ICS9FG107
I²C Table: Frequency Select Readback Register
Byte 3
Pin #
Name
Control
Function
Bit 7
27
SEL14M_25M#¹ _{State of pin 27}
(FS3)
Bit 6
5
FS2¹
State of pin 6
Bit 5
44
FS1¹
State of pin 44
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
7
FS0¹
State of pin 7
26
SPREAD¹ State of pin 26
RESERVED
RESERVED
45
DWNSPRD^{1 State of pin 45}
Type
R
R
R
R
R
R
R
R
0
1
PWD
Pin 27
See Frequency
Selection Table, Page 1
Pin 5
Pin 44
Off
On
RESERVED
RESERVED
Down
Center
Pin 7
Pin 26
X
X
Pin 45
Notes:
1. These read-only bits always reflect the latched state of the corresponding pins at power up.
I²C Table: Vendor & Revision ID Register
Byte 4
Pin #
Name
Control
Type
0
Function
Bit 7
-
RID3
R
-
Bit 6
-
Bit 5
-
RID2
RID1
REVISION ID
R
R
-
-
Bit 4
-
RID0
R
-
Bit 3
-
VID3
R
-
Bit 2
-
Bit 1
-
VID2
VENDOR ID
R
-
VID1
R
-
Bit 0
-
VID0
R
-
1
PWD
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
1
I²C Table: DEVICE ID
Byte 5
Pin #
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Name
Control
Function
Device ID = 07 Hex
Bit 7 is MSB
Type
R
R
R
R
R
R
R
R
0
1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PWD
0
0
0
0
0
1
1
1
0863C—11/22/04
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